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Department of Computer Science and Technology

Course pages 2020–21



A megafunction is a pre-built module that performs a commonly required function. This avoids the developer having to write these modules themselves, hence saving a lot of development time. Altera ship several megafunctions with Quartus covering a range of tasks such as a FIFO buffer, arithmetic units - add, multiply, divide etc., several DSP modules, and many more.

Adding a PLL Megafunction

The tPad provides 2 clock oscillators, one at 50MHz and the other at 27MHz. However, in your designs you may find you need to produce a modified clock signal e.g. with a different frequency or phase. This can be done using a PLL (Phase-Locked-Loop) megafunction.

Begin in Quartus by selecting Tools | IP Catalog from the menu. This will open a new page titled "IP Catalog" on the right side of the quartus main window. Type "ALTPLL" into the search box just below the title and then double-click on "ALTPLL" in the tree below.

In the box that appears, give the file to be created a name e.g. pll.v, ensuring it is saved in the working directory for your project. So don't selete the pre-completed path, just add pll.v to the end. Then select Verilog under "IP variation file type" and click OK.

A wizard will appear. On page 1, set the Device speed grade to 7 and set the frequency of the inclock0 input to 50 MHz. Leave the other settings as default, and click Next.

Un-tick all the boxes on page 2 of the wizard. These features are not required. Click Next until you reach page 6.

You should now be on the page titled c0 - Core/External Output Clock. This page allows you to specify parameters for the first output clock of the component. To change the frequency, you can either select Enter output clock parameters and enter a pair of integers into Clock Multiplication factor and Clock Division factor or select Enter output clock frequency and enter the desired clock rate. Set up the clock as required (including any phase shift) and click Next.

If you want two or more clocks you will need to click Use this clock on subsequent pages and then set them up as described above. When you have set up all of the clocks that you require, click Finish to move to page 12 of the wizard, which displays a list of the files that will be created. Click Finish again to create the megafunction. In the dialog that appears click Yes to add the megafunction to your project.

The module definition can be found in the file you specified. An example instantiation of the megafunction is:

pll altpll(.inclk0(CLOCK_50), .c0(clk0), .c1(clk1));