Computer Laboratory

I'm a postdoctoral researcher in the University of Cambridge Computer Laboratory working in the Computer Architecture Group on the CTSRD project, which is applying a clean-slate approach to computer design for the purpose of security, by implementing CHERI, a RISC capability machine. CHERI comprises a 64-bit RISC processor that implements the MIPS4K instruction set, boots FreeBSD with capability support, and runs on Altera and Xilinx FPGAs.

I was previously on the BIMPA project. BIMPA aimed to build a supercomputer capable simulating a substantial portion of the neurons in the human brain in real time. I'm working on constructing the supercomputer from an array of FPGA boards, with particular interests in the high speed interconnect and scaling to large systems.

I've also been designing and building a variety of FPGA systems including all of our hardware research platforms, including all the mechanical design and systems integration.

DE4 tablet booting CHERI

For my PhD I was looking at the security of consumer computer hardware devices such as smartcards, in close collaboration with the Security Group. I'm particularly interested in low-cost electromagnetic attacks of security hardware.


  • David Chisnall, Brooks Davis, Khilan Gudka, David Brazdil, Alexandre Joannou, Jonathan Woodruff, A. Theodore Markettos, J. Edward Maste, Robert Norton, Stacey Son, Michael Roe, Simon W. Moore, Peter G. Neumann, Ben Laurie, and Robert N. M. Watson. CHERI-JNI: Sinking the Java security model into the C. Proceedings of the 22nd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2017). Xi'an, China, April 8–12, 2017. (PDF)
  • Robert N.M. Watson, Robert M. Norton, Jonathan Woodruff, Simon W. Moore, Peter G. Neumann, Jonathan Anderson, David Chisnall, Brooks Davis, Ben Laurie, Michael Roe, Nirav H. Dave, Khilan Gudka, Alexandre Joannou, A. Theodore Markettos, Ed Maste, Ste Fast Protection-Domain Crossing in the CHERI Capability-System Architecture. IEEE Micro vol. 36 no. 5, p. 38-49, Sept.-Oct., 2016.
  • A. Theodore Markettos, Simon W. Moore, Brian D. Jones, Roy Spliet and Vlad A. Gavrila, Conquering the Complexity Mountain: Full-stack Computer Architecture teaching with FPGAs, 11th European Workshop on Microelectronics Education (EWME 2016), Southampton, May 2016. (PDF).
  • A. Theodore Markettos, Paul J. Fox, Simon W. Moore, Andrew W. Moore, Interconnect for commodity FPGA clusters: standardized or customized?, 24th International Conference on Field Programmable Logic and Applications (FPL), September 2014 (PDF).
  • Paul J. Fox, A. Theodore Markettos and Simon W. Moore, Reliably Prototyping Large SoCs Using FPGA Clusters, 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), June 2014 (PDF)
  • Matthew Naylor, Paul J Fox, A Theodore Markettos and Simon W Moore, Managing the FPGA Memory Wall: Custom Computing or Vector Processing?, 23rd International Conference on Field Programmable Logic and Applications (FPL), September 2013 (PDF)
  • Simon W. Moore, Paul J. Fox, Steven J. T. Marsh, A. Theodore Markettos and Alan Mujumdar, Bluehive - A Field-Programmable Custom Computing Machine for Extreme-Scale Real-Time Neural Network Simulation. In proceedings of Field-Programmable Custom Computing Machines (FCCM), April 2012. PDF
  • A. T. Markettos, Active electromagnetic attacks on secure hardware. PhD thesis, University of Cambridge Technical Report 811. Abstract and PDF.
  • A. T. Markettos and S. W. Moore, The Frequency Injection Attack on Ring-Oscillator-Based True Random Number Generators. In proceedings of Cryptographic Hardware and Embedded Systems (CHES), September 2009. LNCS 5747, pp 317-331. corrected PDF (original PDF), slides.
  • H. Li, A. T. Markettos and S. W. Moore, A Security Evaluation Methodology for Smart Cards Against Electromagnetic Analysis. In proceedings of the 39th IEEE International Carnahan Conference on Security Technology (ICCST 2005), October 2005. PDF
  • H. Li, A. T. Markettos and S. W. Moore, Security Evaluation Against Electromagnetic Analysis at Design Time. Cryptographic Hardware and Embedded Systems (CHES), September 2005. PDF
  • A.T. Markettos and S.W. Moore, Electromagnetic Analysis of Synchronous and Asynchronous Circuits using Hard Disc Heads, 16th UK Async. Forum, September 2004. PDF version
  • Equalisation on a custom DSP core, Master's thesis, Cambridge University Engineering Department, June 2002. Report, summary paper.

My personal website is elsewhere.