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Course pages 2022–23

ECAD and Architecture Practical Classes

Exercise 8 (optional): Etch-a-sketch (or Pong) on FPGA

Adding your Verilog components

Now is time to add your rotary controllers and shift register to your Qsys project, so we can access them from Clarvi.

Copy the Verilog for the rotary encoders and shift register from Exercise 2b into your clarvi_fpga folder from Exercise 5. Also copy the files ending _hw.tcl - these are the definitions for your Qsys components.

Start Qsys and open clarvi_soc.qsys. If you have Qsys already open, go to File | Refresh System (or press F5) to cause Qsys to rescan and add them to its library of components.

In Qsys you should see the rotary encoder (and shift register if you made a Qsys component) appear as components in the IP Catalog on the left. You can double click to add one instance to your design. Add a rotary controller and move it next to your leftdial_pio with the up/down buttons on the toolbar.

Connect up the clock and reset as your other components. Export the rotary_in and rotary_event ports of the rotary controller. Finally join the rotary_pos output port of the rotary controller to the external_connection of the leftdial_pio.

Add a second rotary controller and connect it to the rightdial_pio.

Add the shift register Qsys component and connect it to the buttons_pio.

Your system should like similar to the image below:

Rotary controllers and shift register in Qsys on Clarvi

We have now finished adding hardware to the system so we can generate the system. Before doing so, go to Generate | Instantiation Template and copy the code to instantiate the Qsys project in your top level Verilog. Then you can Generate HDL...

While it is generating, go back to Quartus and open Using the code you copied, adjust the instantiation of the Qsys project to add any extra ports that are now present on the Qsys project (it is probably safer to cut and paste ports into the existing declaration than paste in a complete new declaration from scratch - making an error with the memory or reset connections can be time consuming to debug).

Wire the ports from the Qsys instantiation as follows (your names may be slightly different):

Qsys portI/O pin
rotaryctl_left_rotary_event_cwDon't connect
rotaryctl_left_rotary_event_ccwDon't connect
rotaryctl_right_rotary_event_cwDon't connect
rotaryctl_right_rotary_event_ccwDon't connect

Adding your software and building the FPGA

Find the path of your Etch A Sketch or Pong code in relation to your clarvi_fpga directory, for example ../../ex6/software. When in your clarvi_fpga directory, change the symlink to point to its mem.hex:

rm mem.hex
ln -s ../../ex6_etchsim/c_program/build/mem.hex mem.hex

and check this symlink works.

Check your software builds correctly, and then it is time to start your FPGA synthesis.

When your build has completed, download to your FPGA and test your code.