Comparative Architectures

Lectures

I hope you enjoy the course. Please feel free to email me if you spot any mistakes or have questions ([Javascript required]).

Notes as printed

Lecture notes

Errata/changes vs. as printed

Lecture 3/4: Advanced pipelining, slide 81 (updated)
Lecture 5-7: Superscalar processors, slide 19 (corrected, the reproduced figure in the old/printed slide has a small error)
Lecture 8/9: Software approaches to ILP, new slide 51 (provides a little more info about Nvidia Denver/Carmel)
Lecture 10: Multithreaded processors, slide 22, typo fixed ("as" -> "at the same time")

Slides for each lecture (1-up)

Lecture 1/2: Introduction, trends and fundamentals
Lecture 3/4: Advanced pipelining
Lecture 5/6/7: Superscalar processors
Lecture 8/9: Software approaches to ILP
Lecture 10: Multithreaded processors
Lecture 11/12: The Memory Hierarchy
Lecture 13: Vector processors and Vector/SIMD instruction set extensions
Lecture 14/15: Multi-core processors
Lecture 16: Special-purpose architectures

I would also recommend watching this lecture from Dr. Sophie Wilson if time permits: (lecture video)

Books

* J. Hennessy and D. Patterson, "Computer Architecture: A Quantitative Approach", Elsevier (6th Edition). (publisher's book page)

Supplementary Information and Further Reading

Here are links to the material referenced in the lectures and one or two other interesting papers. This is simply provided in case you would like to explore further. It is not required reading.

Lecture 1 - Introduction, trends and fundamentals

V. J. Reddi and M. D. Hill, "Accelerator-Level Parallelism" (ACM SIGARCH article, Sept. 2019) (Talk by Mark Hill)

John Hennessy and David Patterson, "A New Golden Age for Computer Architecture: Domain-Specific Hardware/Software Co-Design, Enhanced Security, Open Instruction Sets, and Agile Chip Development", Turing Lecture, delivered at ISCA, 2018. (video)

C. E. Leiserson et al,"There’s plenty of room at the Top: What will drive computer performance after Moore’s law?", Science, 368(6495), June, 2020. (article)

Lecture 2 - Introduction, trends and fundamentals

A. Waterman, K. Asanovic, "The RISC-V Instruction Set Manual", (PDF) (contains interesting history / commentary)

ARM Cortex-A Series Programmer's Guide for ARMv8-A (link)

Lecture 3 and 4 - Advanced Pipelining

CK. Lin and S. J. Tarsa, "Branch prediction is not a solved problem: measurements, opportunities, and future directions", In Proc. IISWC 2019. (article)

Lecture 5 and 6 - Superscalar processors

The Alpha and MIPS processors below are older, but have influenced modern designs. The papers are also full of interesting information and are written in a way that makes them quite accessible.

R. E. Kessler, "The Alpha 21264 microprocessor", IEEE Micro, 19(2), Mar/Apr 1999. (article)

K. C. Yeager, "The MIPS R10000 Superscalar Microprocessor", IEEE Micro, 16(2), Apr 1996. (article)

J. Zhao, B. Korpan, A. Gonzalez, K. Asanovic, "SonicBoom: The 3rd generation Berkely Out-of-Order Machine", (article) (further technical documentation)

D. S. McFarlin, C. Tucker and C. Zilles, "Discerning the Dominant Out-of-Order Performance Advantage: Is it Speculation or Dynamism?" (article)
(An interesting paper that studies where the performance advantages of out-of-order execution come from. )

Lecture 7 and 8 - Software approaches to ILP

L. Codrescu et al., "Hexagon DSP: An architecture optimised for mobile multimedia and communications" (article)

Lecture 9 - Multithreaded processors

Lecture 10 and 11 - The Memory Hierarchy

Lecture 12 - Vector processors and SIMD instruction set extensions

D. Patterson and A. Waterman, "SIMD instructions considered harmful", ACM SigArch, 2017 (article)

M. Voss, "Topics in Loop Vectorization", interesting and useful slides on vectorizing loops, what might limit vectorization etc. (slides)

Lecture 13 and 14 - Multi-core processors

V. Nagarajan, D.J. Sorin, M. D. Hill and D. A. Wood, "A Primer on Memory Consistency and Cache Coherence" (2nd Edition, 2020) (Book PDF)

P. Kongetira, K. Aingaran and K. Olukotun, "Niagara: A 32-way multithreaded SPARC processor", IEEE MICRO, Mar-Apr, 2005 (article)