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Course pages 2020–21

Comparative Architectures

For the final lecture, please watch this lecture from Dr. Sophie Wilson


  • Lecture: Multi-core processors (Part 1), slide 25: While describing figure (c) I accidently refer to it as an "inclusive" cache rather than an "exclusive" one.

Notes as printed

Lecture notes (Part 1 of 2)
Lecture notes (Part 2 of 2)

Slides for each lecture (1-up)

Lectures 1 and 2: Introduction, trends and fundamentals
Lectures 3 and 4: Advanced pipelining
Lectures 5 and 6: Superscalar processors
Lecture 7 (2 x 50min): Software approaches to ILP
Lecture 8: Multithreaded processors
Lecture 9 and 10: The Memory Hierarchy
Lecture 11: Vector processors and SIMD instruction set extensions
Lecture 12 and 13: Multi-core processors
Lecture 14: Special-purpose architectures
Final Lecture: Guest Lecture by Dr. Sophie Wilson

Sophie Wilson has kindly given the final lecture of this course for a number of years. While it is unfortunately not possible to welcome her again this year, I suggest you watch her Wheeler Lecture from 2020. This is very similar to the lecture she would normally give and is a great way to finish the course. I very much hope you enjoy the course and Sophie's lecture.

Do feel free to email me if I can help in any way or if you spot any issues with the slides or recordings, thank you ([Javascript required]).

Robert Mullins


* J. Hennessy and D. Patterson, "Computer Architecture: A Quantitative Approach", Elsevier (6th Edition). (publisher's book page)

Supplementary Information and Further Reading

Here are links to the material referenced in the lectures and one or two other interesting papers. This is simply provided in case you would like to explore further. It is not required reading.

Lecture 1 - Introduction, trends and fundamentals

V. J. Reddi and M. D. Hill, "Accelerator-Level Parallelism" (ACM SIGARCH article, Sept. 2019) (Talk by Mark Hill)

John Hennessy and David Patterson, "A New Golden Age for Computer Architecture: Domain-Specific Hardware/Software Co-Design, Enhanced Security, Open Instruction Sets, and Agile Chip Development", Turing Lecture, delivered at ISCA, 2018. (video)

C. E. Leiserson et al,"There’s plenty of room at the Top: What will drive computer performance after Moore’s law?", Science, 368(6495), June, 2020. (article)

Lecture 2 - Introduction, trends and fundamentals

A. Waterman, K. Asanovic, "The RISC-V Instruction Set Manual", (PDF) (contains interesting history / commentary)

ARM Cortex-A Series Programmer's Guide for ARMv8-A (link)

Lecture 3 and 4 - Advanced Pipelining

CK. Lin and S. J. Tarsa, "Branch prediction is not a solved problem: measurements, opportunities, and future directions", In Proc. IISWC 2019. (article)

Lecture 5 and 6 - Superscalar processors

The Alpha and MIPS processors below are older, but have influenced modern designs. The papers are also full of interesting information and are written in a way that makes them quite accessible.

R. E. Kessler, "The Alpha 21264 microprocessor", IEEE Micro, 19(2), Mar/Apr 1999. (article)

K. C. Yeager, "The MIPS R10000 Superscalar Microprocessor", IEEE Micro, 16(2), Apr 1996. (article)

J. Zhao, B. Korpan, A. Gonzalez, K. Asanovic, "SonicBoom: The 3rd generation Berkely Out-of-Order Machine", (article) (further technical documentation)

D. S. McFarlin, C. Tucker and C. Zilles, "Discerning the Dominant Out-of-Order Performance Advantage: Is it Speculation or Dynamism?" (article)
(An interesting paper that studies where the performance advantages of out-of-order execution come from. )

Lecture 7 - Software approaches to ILP

L. Codrescu et al., "Hexagon DSP: An architecture optimised for mobile multimedia and communications" (article)

Lecture 8 - Multithreaded processors

Lecture 9 and 10 - The Memory Hierarchy

Lecture 11 - Vector processors and SIMD instruction set extensions

D. Patterson and A. Waterman, "SIMD instructions considered harmful", ACM SigArch, 2017 (article)

Lecture 12/13 - Multi-core processors

P. Kongetira, K. Aingaran and K. Olukotun, "Niagara: A 32-way multithreaded SPARC processor", IEEE MICRO, Mar-Apr, 2005 (article)