#include "dwc_otg_core_if.h"
Go to the source code of this file.
Data Structures | |
struct | dwc_otg_core_global_regs |
DWC_otg Core registers . More... | |
union | gotgctl_data |
This union represents the bit fields of the Core OTG Control and Status Register (GOTGCTL). More... | |
union | gotgint_data |
This union represents the bit fields of the Core OTG Interrupt Register (GOTGINT). More... | |
union | gahbcfg_data |
This union represents the bit fields of the Core AHB Configuration Register (GAHBCFG). More... | |
union | gusbcfg_data |
This union represents the bit fields of the Core USB Configuration Register (GUSBCFG). More... | |
union | glpmctl_data |
This union represents the bit fields of the Core LPM Configuration Register (GLPMCFG). More... | |
union | grstctl_data |
This union represents the bit fields of the Core Reset Register (GRSTCTL). More... | |
union | gintmsk_data |
This union represents the bit fields of the Core Interrupt Mask Register (GINTMSK). More... | |
union | gintsts_data |
This union represents the bit fields of the Core Interrupt Register (GINTSTS). More... | |
union | device_grxsts_data |
This union represents the bit fields in the Device Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 element then read out the bits using the bit elements. More... | |
union | host_grxsts_data |
This union represents the bit fields in the Host Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 element then read out the bits using the bit elements. More... | |
union | fifosize_data |
This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). More... | |
union | gnptxsts_data |
This union represents the bit fields in the Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS). More... | |
union | dtxfsts_data |
This union represents the bit fields in the Transmit FIFO Status Register (DTXFSTS). More... | |
union | gi2cctl_data |
This union represents the bit fields in the I2C Control Register (I2CCTL). More... | |
union | hwcfg1_data |
This union represents the bit fields in the User HW Config1 Register. More... | |
union | hwcfg2_data |
This union represents the bit fields in the User HW Config2 Register. More... | |
union | hwcfg3_data |
This union represents the bit fields in the User HW Config3 Register. More... | |
union | hwcfg4_data |
This union represents the bit fields in the User HW Config4 Register. More... | |
struct | dwc_otg_dev_global_regs |
Device Global Registers. More... | |
union | dcfg_data |
This union represents the bit fields in the Device Configuration Register. More... | |
union | dctl_data |
This union represents the bit fields in the Device Control Register. More... | |
union | dsts_data |
This union represents the bit fields in the Device Status Register. More... | |
union | diepint_data |
This union represents the bit fields in the Device IN EP Interrupt Register and the Device IN EP Common Mask Register. More... | |
union | doepint_data |
This union represents the bit fields in the Device OUT EP Interrupt Registerand Device OUT EP Common Interrupt Mask Register. More... | |
union | daint_data |
This union represents the bit fields in the Device All EP Interrupt and Mask Registers. More... | |
union | dtknq1_data |
This union represents the bit fields in the Device IN Token Queue Read Registers. More... | |
union | dthrctl_data |
This union represents Threshold control Register
| |
struct | dwc_otg_dev_in_ep_regs |
Device Logical IN Endpoint-Specific Registers. More... | |
struct | dwc_otg_dev_out_ep_regs |
Device Logical OUT Endpoint-Specific Registers. More... | |
union | depctl_data |
This union represents the bit fields in the Device EP Control Register. More... | |
union | deptsiz_data |
This union represents the bit fields in the Device EP Transfer Size Register. More... | |
union | deptsiz0_data |
This union represents the bit fields in the Device EP 0 Transfer Size Register. More... | |
union | dev_dma_desc_sts |
This union represents the bit fields in the DMA Descriptor status quadlet. More... | |
struct | dwc_otg_dev_dma_desc |
DMA Descriptor structure. More... | |
struct | dwc_otg_dev_if |
The dwc_otg_dev_if structure contains information needed to manage the DWC_otg controller acting in device mode. More... | |
struct | dwc_otg_host_global_regs |
The Host Global Registers structure defines the size and relative field offsets for the Host Mode Global Registers. More... | |
union | hcfg_data |
This union represents the bit fields in the Host Configuration Register. More... | |
union | hfir_data |
This union represents the bit fields in the Host Frame Remaing/Number Register. More... | |
union | hfnum_data |
This union represents the bit fields in the Host Frame Remaing/Number Register. More... | |
union | hptxsts_data |
union | hprt0_data |
This union represents the bit fields in the Host Port Control and Status Register. More... | |
union | haint_data |
This union represents the bit fields in the Host All Interrupt Register. More... | |
union | haintmsk_data |
This union represents the bit fields in the Host All Interrupt Register. More... | |
struct | dwc_otg_hc_regs |
Host Channel Specific Registers. More... | |
union | hcchar_data |
This union represents the bit fields in the Host Channel Characteristics Register. More... | |
union | hcsplt_data |
union | hcint_data |
This union represents the bit fields in the Host All Interrupt Register. More... | |
union | hcintmsk_data |
This union represents the bit fields in the Host Channel Interrupt Mask Register. More... | |
union | hctsiz_data |
This union represents the bit fields in the Host Channel Transfer Size Register. More... | |
union | hcdma_data |
This union represents the bit fields in the Host DMA Address Register used in Descriptor DMA mode. More... | |
union | host_dma_desc_sts |
This union represents the bit fields in the DMA Descriptor status quadlet for host mode. More... | |
struct | dwc_otg_host_dma_desc |
Host-mode DMA Descriptor structure. More... | |
struct | dwc_otg_host_if |
OTG Host Interface Structure. More... | |
union | pcgcctl_data |
This union represents the bit fields in the Power and Clock Gating Control Register. More... | |
Defines | |
#define | DWC_GLBINTRMASK 0x0001 |
#define | DWC_DMAENABLE 0x0020 |
#define | DWC_NPTXEMPTYLVL_EMPTY 0x0080 |
#define | DWC_NPTXEMPTYLVL_HALFEMPTY 0x0000 |
#define | DWC_PTXEMPTYLVL_EMPTY 0x0100 |
#define | DWC_PTXEMPTYLVL_HALFEMPTY 0x0000 |
#define | DWC_SLAVE_ONLY_ARCH 0 |
#define | DWC_EXT_DMA_ARCH 1 |
#define | DWC_INT_DMA_ARCH 2 |
#define | DWC_MODE_HNP_SRP_CAPABLE 0 |
#define | DWC_MODE_SRP_ONLY_CAPABLE 1 |
#define | DWC_MODE_NO_HNP_SRP_CAPABLE 2 |
#define | DWC_MODE_SRP_CAPABLE_DEVICE 3 |
#define | DWC_MODE_NO_SRP_CAPABLE_DEVICE 4 |
#define | DWC_MODE_SRP_CAPABLE_HOST 5 |
#define | DWC_MODE_NO_SRP_CAPABLE_HOST 6 |
#define | DWC_GAHBCFG_GLBINT_ENABLE 1 |
#define | DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0 |
#define | DWC_GAHBCFG_INT_DMA_BURST_INCR 1 |
#define | DWC_GAHBCFG_INT_DMA_BURST_INCR4 3 |
#define | DWC_GAHBCFG_INT_DMA_BURST_INCR8 5 |
#define | DWC_GAHBCFG_INT_DMA_BURST_INCR16 7 |
#define | DWC_GAHBCFG_DMAENABLE 1 |
#define | DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1 |
#define | DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 |
#define | DWC_SOF_INTR_MASK 0x0008 |
#define | DWC_HOST_MODE 1 |
#define | DWC_STS_DATA_UPDT 0x2 |
#define | DWC_STS_XFER_COMP 0x3 |
#define | DWC_DSTS_GOUT_NAK 0x1 |
#define | DWC_DSTS_SETUP_COMP 0x4 |
#define | DWC_DSTS_SETUP_UPDT 0x6 |
#define | DWC_GRXSTS_PKTSTS_IN 0x2 |
#define | DWC_GRXSTS_PKTSTS_IN_XFER_COMP 0x3 |
#define | DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5 |
#define | DWC_GRXSTS_PKTSTS_CH_HALTED 0x7 |
#define | DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0 |
#define | DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1 |
#define | DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2 |
#define | DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3 |
#define | DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4 |
#define | DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5 |
#define | DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6 |
#define | DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0 |
#define | DWC_HWCFG2_HS_PHY_TYPE_UTMI 1 |
#define | DWC_HWCFG2_HS_PHY_TYPE_ULPI 2 |
#define | DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3 |
#define | DWC_DCFG_SEND_STALL 1 |
#define | DWC_DCFG_FRAME_INTERVAL_80 0 |
#define | DWC_DCFG_FRAME_INTERVAL_85 1 |
#define | DWC_DCFG_FRAME_INTERVAL_90 2 |
#define | DWC_DCFG_FRAME_INTERVAL_95 3 |
#define | DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 |
#define | DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 |
#define | DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2 |
#define | DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3 |
#define | DWC_DEP0CTL_MPS_64 0 |
#define | DWC_DEP0CTL_MPS_32 1 |
#define | DWC_DEP0CTL_MPS_16 2 |
#define | DWC_DEP0CTL_MPS_8 3 |
#define | BS_HOST_READY 0x0 |
Buffer status definitions. | |
#define | BS_DMA_BUSY 0x1 |
#define | BS_DMA_DONE 0x2 |
#define | BS_HOST_BUSY 0x3 |
#define | RTS_SUCCESS 0x0 |
Receive/Transmit status definitions. | |
#define | RTS_BUFFLUSH 0x1 |
#define | RTS_RESERVED 0x2 |
#define | RTS_BUFERR 0x3 |
#define | DWC_DEV_GLOBAL_REG_OFFSET 0x800 |
#define | DWC_DEV_IN_EP_REG_OFFSET 0x900 |
#define | DWC_EP_REG_OFFSET 0x20 |
#define | DWC_DEV_OUT_EP_REG_OFFSET 0xB00 |
#define | DWC_HCFG_30_60_MHZ 0 |
#define | DWC_HCFG_48_MHZ 1 |
#define | DWC_HCFG_6_MHZ 2 |
#define | DWC_HFNUM_MAX_FRNUM 0x3FFF |
#define | DWC_HPRT0_PRTSPD_HIGH_SPEED 0 |
#define | DWC_HPRT0_PRTSPD_FULL_SPEED 1 |
#define | DWC_HPRT0_PRTSPD_LOW_SPEED 2 |
#define | DWC_HCSPLIT_XACTPOS_MID 0 |
#define | DWC_HCSPLIT_XACTPOS_END 1 |
#define | DWC_HCSPLIT_XACTPOS_BEGIN 2 |
#define | DWC_HCSPLIT_XACTPOS_ALL 3 |
#define | DWC_HCTSIZ_DATA0 0 |
#define | DWC_HCTSIZ_DATA1 2 |
#define | DWC_HCTSIZ_DATA2 1 |
#define | DWC_HCTSIZ_MDATA 3 |
#define | DWC_HCTSIZ_SETUP 3 |
#define | DMA_DESC_STS_PKTERR 1 |
#define | MAX_DMA_DESC_SIZE 131071 |
#define | MAX_DMA_DESC_NUM_GENERIC 64 |
#define | MAX_DMA_DESC_NUM_HS_ISOC 256 |
#define | MAX_FRLIST_EN_NUM 64 |
#define | DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400 |
#define | DWC_OTG_HOST_PORT_REGS_OFFSET 0x440 |
#define | DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500 |
#define | DWC_OTG_CHAN_REGS_OFFSET 0x20 |
Typedefs | |
typedef dwc_otg_core_global_regs | dwc_otg_core_global_regs_t |
DWC_otg Core registers . | |
typedef gotgctl_data | gotgctl_data_t |
This union represents the bit fields of the Core OTG Control and Status Register (GOTGCTL). | |
typedef gotgint_data | gotgint_data_t |
This union represents the bit fields of the Core OTG Interrupt Register (GOTGINT). | |
typedef gahbcfg_data | gahbcfg_data_t |
This union represents the bit fields of the Core AHB Configuration Register (GAHBCFG). | |
typedef gusbcfg_data | gusbcfg_data_t |
This union represents the bit fields of the Core USB Configuration Register (GUSBCFG). | |
typedef glpmctl_data | glpmcfg_data_t |
This union represents the bit fields of the Core LPM Configuration Register (GLPMCFG). | |
typedef grstctl_data | grstctl_t |
This union represents the bit fields of the Core Reset Register (GRSTCTL). | |
typedef gintmsk_data | gintmsk_data_t |
This union represents the bit fields of the Core Interrupt Mask Register (GINTMSK). | |
typedef gintsts_data | gintsts_data_t |
This union represents the bit fields of the Core Interrupt Register (GINTSTS). | |
typedef device_grxsts_data | device_grxsts_data_t |
This union represents the bit fields in the Device Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 element then read out the bits using the bit elements. | |
typedef host_grxsts_data | host_grxsts_data_t |
This union represents the bit fields in the Host Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 element then read out the bits using the bit elements. | |
typedef fifosize_data | fifosize_data_t |
This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). | |
typedef gnptxsts_data | gnptxsts_data_t |
This union represents the bit fields in the Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS). | |
typedef dtxfsts_data | dtxfsts_data_t |
This union represents the bit fields in the Transmit FIFO Status Register (DTXFSTS). | |
typedef gi2cctl_data | gi2cctl_data_t |
This union represents the bit fields in the I2C Control Register (I2CCTL). | |
typedef hwcfg1_data | hwcfg1_data_t |
This union represents the bit fields in the User HW Config1 Register. | |
typedef hwcfg2_data | hwcfg2_data_t |
This union represents the bit fields in the User HW Config2 Register. | |
typedef hwcfg3_data | hwcfg3_data_t |
This union represents the bit fields in the User HW Config3 Register. | |
typedef hwcfg4_data | hwcfg4_data_t |
This union represents the bit fields in the User HW Config4 Register. | |
typedef dwc_otg_dev_global_regs | dwc_otg_device_global_regs_t |
Device Global Registers. | |
typedef dcfg_data | dcfg_data_t |
This union represents the bit fields in the Device Configuration Register. | |
typedef dctl_data | dctl_data_t |
This union represents the bit fields in the Device Control Register. | |
typedef dsts_data | dsts_data_t |
This union represents the bit fields in the Device Status Register. | |
typedef diepint_data | diepint_data_t |
This union represents the bit fields in the Device IN EP Interrupt Register and the Device IN EP Common Mask Register. | |
typedef diepint_data | diepmsk_data_t |
This union represents the bit fields in the Device IN EP Common/Dedicated Interrupt Mask Register. | |
typedef doepint_data | doepint_data_t |
This union represents the bit fields in the Device OUT EP Interrupt Registerand Device OUT EP Common Interrupt Mask Register. | |
typedef doepint_data | doepmsk_data_t |
This union represents the bit fields in the Device OUT EP Common/Dedicated Interrupt Mask Register. | |
typedef daint_data | daint_data_t |
This union represents the bit fields in the Device All EP Interrupt and Mask Registers. | |
typedef dtknq1_data | dtknq1_data_t |
This union represents the bit fields in the Device IN Token Queue Read Registers. | |
typedef dthrctl_data | dthrctl_data_t |
This union represents Threshold control Register
| |
typedef dwc_otg_dev_in_ep_regs | dwc_otg_dev_in_ep_regs_t |
Device Logical IN Endpoint-Specific Registers. | |
typedef dwc_otg_dev_out_ep_regs | dwc_otg_dev_out_ep_regs_t |
Device Logical OUT Endpoint-Specific Registers. | |
typedef depctl_data | depctl_data_t |
This union represents the bit fields in the Device EP Control Register. | |
typedef deptsiz_data | deptsiz_data_t |
This union represents the bit fields in the Device EP Transfer Size Register. | |
typedef deptsiz0_data | deptsiz0_data_t |
This union represents the bit fields in the Device EP 0 Transfer Size Register. | |
typedef dev_dma_desc_sts | dev_dma_desc_sts_t |
This union represents the bit fields in the DMA Descriptor status quadlet. | |
typedef dwc_otg_dev_dma_desc | dwc_otg_dev_dma_desc_t |
DMA Descriptor structure. | |
typedef dwc_otg_dev_if | dwc_otg_dev_if_t |
The dwc_otg_dev_if structure contains information needed to manage the DWC_otg controller acting in device mode. | |
typedef dwc_otg_host_global_regs | dwc_otg_host_global_regs_t |
The Host Global Registers structure defines the size and relative field offsets for the Host Mode Global Registers. | |
typedef hcfg_data | hcfg_data_t |
This union represents the bit fields in the Host Configuration Register. | |
typedef hfir_data | hfir_data_t |
This union represents the bit fields in the Host Frame Remaing/Number Register. | |
typedef hfnum_data | hfnum_data_t |
This union represents the bit fields in the Host Frame Remaing/Number Register. | |
typedef hptxsts_data | hptxsts_data_t |
typedef hprt0_data | hprt0_data_t |
This union represents the bit fields in the Host Port Control and Status Register. | |
typedef haint_data | haint_data_t |
This union represents the bit fields in the Host All Interrupt Register. | |
typedef haintmsk_data | haintmsk_data_t |
This union represents the bit fields in the Host All Interrupt Register. | |
typedef dwc_otg_hc_regs | dwc_otg_hc_regs_t |
Host Channel Specific Registers. | |
typedef hcchar_data | hcchar_data_t |
This union represents the bit fields in the Host Channel Characteristics Register. | |
typedef hcsplt_data | hcsplt_data_t |
typedef hcint_data | hcint_data_t |
This union represents the bit fields in the Host All Interrupt Register. | |
typedef hcintmsk_data | hcintmsk_data_t |
This union represents the bit fields in the Host Channel Interrupt Mask Register. | |
typedef hctsiz_data | hctsiz_data_t |
This union represents the bit fields in the Host Channel Transfer Size Register. | |
typedef hcdma_data | hcdma_data_t |
This union represents the bit fields in the Host DMA Address Register used in Descriptor DMA mode. | |
typedef host_dma_desc_sts | host_dma_desc_sts_t |
This union represents the bit fields in the DMA Descriptor status quadlet for host mode. | |
typedef dwc_otg_host_dma_desc | dwc_otg_host_dma_desc_t |
Host-mode DMA Descriptor structure. | |
typedef dwc_otg_host_if | dwc_otg_host_if_t |
OTG Host Interface Structure. | |
typedef pcgcctl_data | pcgcctl_data_t |
This union represents the bit fields in the Power and Clock Gating Control Register. |
The application interfaces with the HS OTG core by reading from and writing to the Control and Status Register (CSR) space through the AHB Slave interface. These registers are 32 bits wide, and the addresses are 32-bit-block aligned. CSRs are classified as follows:
Only the Core Global registers can be accessed in both Device and Host modes. When the HS OTG core is operating in one mode, either Device or Host, the application must not access registers from the other mode. When the core switches from one mode to another, the registers in the new mode of operation must be reprogrammed as they would be after a power-on reset.
Definition in file dwc_otg_regs.h.
typedef struct dwc_otg_core_global_regs dwc_otg_core_global_regs_t |
DWC_otg Core registers .
The dwc_otg_core_global_regs structure defines the size and relative field offsets for the Core Global registers.
typedef union gotgctl_data gotgctl_data_t |
This union represents the bit fields of the Core OTG Control and Status Register (GOTGCTL).
Set the bits using the bit fields then write the d32 value to the register.
typedef union gotgint_data gotgint_data_t |
This union represents the bit fields of the Core OTG Interrupt Register (GOTGINT).
Set/clear the bits using the bit fields then write the d32 value to the register.
typedef union gahbcfg_data gahbcfg_data_t |
This union represents the bit fields of the Core AHB Configuration Register (GAHBCFG).
Set/clear the bits using the bit fields then write the d32 value to the register.
typedef union gusbcfg_data gusbcfg_data_t |
This union represents the bit fields of the Core USB Configuration Register (GUSBCFG).
Set the bits using the bit fields then write the d32 value to the register.
typedef union glpmctl_data glpmcfg_data_t |
This union represents the bit fields of the Core LPM Configuration Register (GLPMCFG).
Set the bits using bit fields then write the d32 value to the register.
typedef union grstctl_data grstctl_t |
This union represents the bit fields of the Core Reset Register (GRSTCTL).
Set/clear the bits using the bit fields then write the d32 value to the register.
typedef union gintmsk_data gintmsk_data_t |
This union represents the bit fields of the Core Interrupt Mask Register (GINTMSK).
Set/clear the bits using the bit fields then write the d32 value to the register.
typedef union gintsts_data gintsts_data_t |
This union represents the bit fields of the Core Interrupt Register (GINTSTS).
Set/clear the bits using the bit fields then write the d32 value to the register.
typedef union fifosize_data fifosize_data_t |
This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, GNPTXFSIZ, DPTXFSIZn, DIEPTXFn).
Read the register into the d32 element then read out the bits using the bit elements.
typedef union gnptxsts_data gnptxsts_data_t |
This union represents the bit fields in the Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS).
Read the register into the d32 element then read out the bits using the bit elements.
typedef union dtxfsts_data dtxfsts_data_t |
This union represents the bit fields in the Transmit FIFO Status Register (DTXFSTS).
Read the register into the d32 element then read out the bits using the bit elements.
typedef union gi2cctl_data gi2cctl_data_t |
This union represents the bit fields in the I2C Control Register (I2CCTL).
Read the register into the d32 element then read out the bits using the bit elements.
typedef union hwcfg1_data hwcfg1_data_t |
This union represents the bit fields in the User HW Config1 Register.
Read the register into the d32 element then read out the bits using the bit elements.
typedef union hwcfg2_data hwcfg2_data_t |
This union represents the bit fields in the User HW Config2 Register.
Read the register into the d32 element then read out the bits using the bit elements.
typedef union hwcfg3_data hwcfg3_data_t |
This union represents the bit fields in the User HW Config3 Register.
Read the register into the d32 element then read out the bits using the bit elements.
typedef union hwcfg4_data hwcfg4_data_t |
This union represents the bit fields in the User HW Config4 Register.
Read the register into the d32 element then read out the bits using the bit elements.
typedef struct dwc_otg_dev_global_regs dwc_otg_device_global_regs_t |
Device Global Registers.
Offsets 800h-BFFh
The following structures define the size and relative field offsets for the Device Mode Registers.
These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown.
typedef union dcfg_data dcfg_data_t |
This union represents the bit fields in the Device Configuration Register.
Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the dcfg register.
typedef union dctl_data dctl_data_t |
This union represents the bit fields in the Device Control Register.
Read the register into the d32 member then set/clear the bits using the bit elements.
typedef union dsts_data dsts_data_t |
This union represents the bit fields in the Device Status Register.
Read the register into the d32 member then set/clear the bits using the bit elements.
typedef union diepint_data diepint_data_t |
This union represents the bit fields in the Device IN EP Interrupt Register and the Device IN EP Common Mask Register.
typedef union doepint_data doepint_data_t |
This union represents the bit fields in the Device OUT EP Interrupt Registerand Device OUT EP Common Interrupt Mask Register.
typedef union daint_data daint_data_t |
This union represents the bit fields in the Device All EP Interrupt and Mask Registers.
typedef union dtknq1_data dtknq1_data_t |
This union represents the bit fields in the Device IN Token Queue Read Registers.
typedef union dthrctl_data dthrctl_data_t |
This union represents Threshold control Register
typedef struct dwc_otg_dev_in_ep_regs dwc_otg_dev_in_ep_regs_t |
Device Logical IN Endpoint-Specific Registers.
Offsets 900h-AFCh
There will be one set of endpoint registers per logical endpoint implemented.
These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown.
typedef struct dwc_otg_dev_out_ep_regs dwc_otg_dev_out_ep_regs_t |
Device Logical OUT Endpoint-Specific Registers.
Offsets: B00h-CFCh
There will be one set of endpoint registers per logical endpoint implemented.
These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown.
typedef union depctl_data depctl_data_t |
This union represents the bit fields in the Device EP Control Register.
Read the register into the d32 member then set/clear the bits using the bit elements.
typedef union deptsiz_data deptsiz_data_t |
This union represents the bit fields in the Device EP Transfer Size Register.
Read the register into the d32 member then set/clear the bits using the bit elements.
typedef union deptsiz0_data deptsiz0_data_t |
This union represents the bit fields in the Device EP 0 Transfer Size Register.
Read the register into the d32 member then set/clear the bits using the bit elements.
typedef union dev_dma_desc_sts dev_dma_desc_sts_t |
This union represents the bit fields in the DMA Descriptor status quadlet.
Read the quadlet into the d32 member then set/clear the bits using the bit, b_iso_out and b_iso_in elements.
typedef struct dwc_otg_dev_dma_desc dwc_otg_dev_dma_desc_t |
DMA Descriptor structure.
DMA Descriptor structure contains two quadlets: Status quadlet and Data buffer pointer.
typedef struct dwc_otg_dev_if dwc_otg_dev_if_t |
The dwc_otg_dev_if structure contains information needed to manage the DWC_otg controller acting in device mode.
It represents the programming view of the device-specific aspects of the controller.
typedef struct dwc_otg_host_global_regs dwc_otg_host_global_regs_t |
The Host Global Registers structure defines the size and relative field offsets for the Host Mode Global Registers.
Host Global Registers offsets 400h-7FFh.
typedef union hcfg_data hcfg_data_t |
This union represents the bit fields in the Host Configuration Register.
Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hcfg register.
typedef union hprt0_data hprt0_data_t |
This union represents the bit fields in the Host Port Control and Status Register.
Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hprt0 register.
typedef struct dwc_otg_hc_regs dwc_otg_hc_regs_t |
Host Channel Specific Registers.
500h-5FCh
typedef union hcchar_data hcchar_data_t |
This union represents the bit fields in the Host Channel Characteristics Register.
Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hcchar register.
typedef union hcintmsk_data hcintmsk_data_t |
This union represents the bit fields in the Host Channel Interrupt Mask Register.
Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hcintmsk register.
typedef union hctsiz_data hctsiz_data_t |
This union represents the bit fields in the Host Channel Transfer Size Register.
Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hcchar register.
typedef union host_dma_desc_sts host_dma_desc_sts_t |
This union represents the bit fields in the DMA Descriptor status quadlet for host mode.
Read the quadlet into the d32 member then set/clear the bits using the bit elements.
typedef struct dwc_otg_host_dma_desc dwc_otg_host_dma_desc_t |
Host-mode DMA Descriptor structure.
DMA Descriptor structure contains two quadlets: Status quadlet and Data buffer pointer.
typedef struct dwc_otg_host_if dwc_otg_host_if_t |
OTG Host Interface Structure.
The OTG Host Interface Structure structure contains information needed to manage the DWC_otg controller acting in host mode. It represents the programming view of the host-specific aspects of the controller.
typedef union pcgcctl_data pcgcctl_data_t |
This union represents the bit fields in the Power and Clock Gating Control Register.
Read the register into the d32 member then set/clear the bits using the bit elements.