dwc_otg_hc_regs Struct Reference

Host Channel Specific Registers. More...

#include <dwc_otg_regs.h>

Data Fields
volatile uint32_t	hcchar
	Host Channel 0 Characteristic Register.
volatile uint32_t	hcsplt
	Host Channel 0 Split Control Register.
volatile uint32_t	hcint
	Host Channel 0 Interrupt Register.
volatile uint32_t	hcintmsk
	Host Channel 0 Interrupt Mask Register.
volatile uint32_t	hctsiz
	Host Channel 0 Transfer Size Register.
volatile uint32_t	hcdma
	Host Channel 0 DMA Address Register.
volatile uint32_t	reserved
volatile uint32_t	hcdmab
	Host Channel 0 DMA Buffer Address Register.

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Detailed Description

Host Channel Specific Registers.

500h-5FCh

Definition at line 1838 of file dwc_otg_regs.h.

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Field Documentation

volatile uint32_t dwc_otg_hc_regs::hcchar

Host Channel 0 Characteristic Register.

Offset: 500h + (chan_num * 20h) + 00h

Definition at line 1841 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_hc_regs::hcsplt

Host Channel 0 Split Control Register.

Offset: 500h + (chan_num * 20h) + 04h

Definition at line 1843 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_hc_regs::hcint

Host Channel 0 Interrupt Register.

Offset: 500h + (chan_num * 20h) + 08h

Definition at line 1845 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_hc_regs::hcintmsk

Host Channel 0 Interrupt Mask Register.

Offset: 500h + (chan_num * 20h) + 0Ch

Definition at line 1847 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_hc_regs::hctsiz

Host Channel 0 Transfer Size Register.

Offset: 500h + (chan_num * 20h) + 10h

Definition at line 1849 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_hc_regs::hcdma

Host Channel 0 DMA Address Register.

Offset: 500h + (chan_num * 20h) + 14h

Definition at line 1851 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_hc_regs::hcdmab

Host Channel 0 DMA Buffer Address Register.

Offset: 500h + (chan_num * 20h) + 1Ch

Definition at line 1854 of file dwc_otg_regs.h.

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The documentation for this struct was generated from the following file:

• dwc_otg_regs.h

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