00001 /* ========================================================================== 00002 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $ 00003 * $Revision: #76 $ 00004 * $Date: 2009/04/02 $ 00005 * $Change: 1224216 $ 00006 * 00007 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, 00008 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless 00009 * otherwise expressly agreed to in writing between Synopsys and you. 00010 * 00011 * The Software IS NOT an item of Licensed Software or Licensed Product under 00012 * any End User Software License Agreement or Agreement for Licensed Product 00013 * with Synopsys or any supplement thereto. You are permitted to use and 00014 * redistribute this Software in source and binary forms, with or without 00015 * modification, provided that redistributions of source code must retain this 00016 * notice. You may not view, use, disclose, copy or distribute this file or 00017 * any information contained herein except pursuant to this license grant from 00018 * Synopsys. If you do not agree with this notice, including the disclaimer 00019 * below, then you are not authorized to use the Software. 00020 * 00021 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS 00022 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00023 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 00024 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, 00025 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 00026 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00027 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00028 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 00029 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 00030 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 00031 * DAMAGE. 00032 * ========================================================================== */ 00033 00034 #ifndef __DWC_OTG_REGS_H__ 00035 #define __DWC_OTG_REGS_H__ 00036 00037 #include "dwc_otg_core_if.h" 00038 00066 /****************************************************************************/ 00071 typedef struct dwc_otg_core_global_regs { 00073 volatile uint32_t gotgctl; 00075 volatile uint32_t gotgint; 00077 volatile uint32_t gahbcfg; 00078 00079 #define DWC_GLBINTRMASK 0x0001 00080 #define DWC_DMAENABLE 0x0020 00081 #define DWC_NPTXEMPTYLVL_EMPTY 0x0080 00082 #define DWC_NPTXEMPTYLVL_HALFEMPTY 0x0000 00083 #define DWC_PTXEMPTYLVL_EMPTY 0x0100 00084 #define DWC_PTXEMPTYLVL_HALFEMPTY 0x0000 00085 00087 volatile uint32_t gusbcfg; 00089 volatile uint32_t grstctl; 00091 volatile uint32_t gintsts; 00093 volatile uint32_t gintmsk; 00095 volatile uint32_t grxstsr; 00097 volatile uint32_t grxstsp; 00099 volatile uint32_t grxfsiz; 00101 volatile uint32_t gnptxfsiz; 00104 volatile uint32_t gnptxsts; 00106 volatile uint32_t gi2cctl; 00108 volatile uint32_t gpvndctl; 00110 volatile uint32_t ggpio; 00112 volatile uint32_t guid; 00114 volatile uint32_t gsnpsid; 00116 volatile uint32_t ghwcfg1; 00118 volatile uint32_t ghwcfg2; 00119 #define DWC_SLAVE_ONLY_ARCH 0 00120 #define DWC_EXT_DMA_ARCH 1 00121 #define DWC_INT_DMA_ARCH 2 00122 00123 #define DWC_MODE_HNP_SRP_CAPABLE 0 00124 #define DWC_MODE_SRP_ONLY_CAPABLE 1 00125 #define DWC_MODE_NO_HNP_SRP_CAPABLE 2 00126 #define DWC_MODE_SRP_CAPABLE_DEVICE 3 00127 #define DWC_MODE_NO_SRP_CAPABLE_DEVICE 4 00128 #define DWC_MODE_SRP_CAPABLE_HOST 5 00129 #define DWC_MODE_NO_SRP_CAPABLE_HOST 6 00130 00132 volatile uint32_t ghwcfg3; 00134 volatile uint32_t ghwcfg4; 00136 volatile uint32_t glpmcfg; 00138 volatile uint32_t reserved[42]; 00140 volatile uint32_t hptxfsiz; 00144 volatile uint32_t dptxfsiz_dieptxf[15]; 00145 } dwc_otg_core_global_regs_t; 00146 00152 typedef union gotgctl_data { 00154 uint32_t d32; 00156 struct { 00157 unsigned sesreqscs:1; 00158 unsigned sesreq:1; 00159 unsigned reserved2_7:6; 00160 unsigned hstnegscs:1; 00161 unsigned hnpreq:1; 00162 unsigned hstsethnpen:1; 00163 unsigned devhnpen:1; 00164 unsigned reserved12_15:4; 00165 unsigned conidsts:1; 00166 unsigned reserved17:1; 00167 unsigned asesvld:1; 00168 unsigned bsesvld:1; 00169 unsigned currmod:1; 00170 unsigned reserved21_31:11; 00171 } b; 00172 } gotgctl_data_t; 00173 00179 typedef union gotgint_data { 00181 uint32_t d32; 00183 struct { 00185 unsigned reserved0_1:2; 00186 00188 unsigned sesenddet:1; 00189 00190 unsigned reserved3_7:5; 00191 00193 unsigned sesreqsucstschng:1; 00195 unsigned hstnegsucstschng:1; 00196 00197 unsigned reserver10_16:7; 00198 00200 unsigned hstnegdet:1; 00202 unsigned adevtoutchng:1; 00204 unsigned debdone:1; 00205 00206 unsigned reserved31_20:12; 00207 00208 } b; 00209 } gotgint_data_t; 00210 00216 typedef union gahbcfg_data { 00218 uint32_t d32; 00220 struct { 00221 unsigned glblintrmsk:1; 00222 #define DWC_GAHBCFG_GLBINT_ENABLE 1 00223 00224 unsigned hburstlen:4; 00225 #define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0 00226 #define DWC_GAHBCFG_INT_DMA_BURST_INCR 1 00227 #define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3 00228 #define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5 00229 #define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7 00230 00231 unsigned dmaenable:1; 00232 #define DWC_GAHBCFG_DMAENABLE 1 00233 unsigned reserved:1; 00234 unsigned nptxfemplvl_txfemplvl:1; 00235 unsigned ptxfemplvl:1; 00236 #define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1 00237 #define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 00238 unsigned reserved9_31:23; 00239 } b; 00240 } gahbcfg_data_t; 00241 00247 typedef union gusbcfg_data { 00249 uint32_t d32; 00251 struct { 00252 unsigned toutcal:3; 00253 unsigned phyif:1; 00254 unsigned ulpi_utmi_sel:1; 00255 unsigned fsintf:1; 00256 unsigned physel:1; 00257 unsigned ddrsel:1; 00258 unsigned srpcap:1; 00259 unsigned hnpcap:1; 00260 unsigned usbtrdtim:4; 00261 unsigned nptxfrwnden:1; 00262 unsigned phylpwrclksel:1; 00263 unsigned otgutmifssel:1; 00264 unsigned ulpi_fsls:1; 00265 unsigned ulpi_auto_res:1; 00266 unsigned ulpi_clk_sus_m:1; 00267 unsigned ulpi_ext_vbus_drv:1; 00268 unsigned ulpi_int_vbus_indicator:1; 00269 unsigned term_sel_dl_pulse:1; 00270 unsigned reserved23_25:3; 00271 unsigned ic_usb_cap:1; 00272 unsigned ic_traffic_pull_remove:1; 00273 unsigned tx_end_delay:1; 00274 unsigned reserved29_31:3; 00275 } b; 00276 } gusbcfg_data_t; 00277 00283 typedef union glpmctl_data { 00285 uint32_t d32; 00287 struct { 00292 unsigned lpm_cap_en:1; 00297 unsigned appl_resp:1; 00306 unsigned hird:4; 00315 unsigned rem_wkup_en:1; 00320 unsigned en_utmi_sleep:1; 00323 unsigned hird_thres:5; 00334 unsigned lpm_resp:2; 00339 unsigned prt_sleep_sts:1; 00344 unsigned sleep_state_resumeok:1; 00350 unsigned lpm_chan_index:4; 00355 unsigned retry_count:3; 00361 unsigned send_lpm:1; 00366 unsigned retry_count_sts:3; 00367 unsigned reserved28_29:2; 00375 unsigned hsic_connect:1; 00379 unsigned inv_sel_hsic:1; 00380 } b; 00381 } glpmcfg_data_t; 00382 00388 typedef union grstctl_data { 00390 uint32_t d32; 00392 struct { 00428 unsigned csftrst:1; 00435 unsigned hsftrst:1; 00444 unsigned hstfrm:1; 00448 unsigned intknqflsh:1; 00463 unsigned rxfflsh:1; 00478 unsigned txfflsh:1; 00479 00495 unsigned txfnum:5; 00497 unsigned reserved11_29:19; 00500 unsigned dmareq:1; 00503 unsigned ahbidle:1; 00504 } b; 00505 } grstctl_t; 00506 00512 typedef union gintmsk_data { 00514 uint32_t d32; 00516 struct { 00517 unsigned reserved0:1; 00518 unsigned modemismatch:1; 00519 unsigned otgintr:1; 00520 unsigned sofintr:1; 00521 unsigned rxstsqlvl:1; 00522 unsigned nptxfempty:1; 00523 unsigned ginnakeff:1; 00524 unsigned goutnakeff:1; 00525 unsigned reserved8:1; 00526 unsigned i2cintr:1; 00527 unsigned erlysuspend:1; 00528 unsigned usbsuspend:1; 00529 unsigned usbreset:1; 00530 unsigned enumdone:1; 00531 unsigned isooutdrop:1; 00532 unsigned eopframe:1; 00533 unsigned reserved16:1; 00534 unsigned epmismatch:1; 00535 unsigned inepintr:1; 00536 unsigned outepintr:1; 00537 unsigned incomplisoin:1; 00538 unsigned incomplisoout:1; 00539 unsigned reserved22_23:2; 00540 unsigned portintr:1; 00541 unsigned hcintr:1; 00542 unsigned ptxfempty:1; 00543 unsigned lpmtranrcvd:1; 00544 unsigned conidstschng:1; 00545 unsigned disconnect:1; 00546 unsigned sessreqintr:1; 00547 unsigned wkupintr:1; 00548 } b; 00549 } gintmsk_data_t; 00555 typedef union gintsts_data { 00557 uint32_t d32; 00558 #define DWC_SOF_INTR_MASK 0x0008 00559 00560 struct { 00561 #define DWC_HOST_MODE 1 00562 unsigned curmode:1; 00563 unsigned modemismatch:1; 00564 unsigned otgintr:1; 00565 unsigned sofintr:1; 00566 unsigned rxstsqlvl:1; 00567 unsigned nptxfempty:1; 00568 unsigned ginnakeff:1; 00569 unsigned goutnakeff:1; 00570 unsigned reserved8:1; 00571 unsigned i2cintr:1; 00572 unsigned erlysuspend:1; 00573 unsigned usbsuspend:1; 00574 unsigned usbreset:1; 00575 unsigned enumdone:1; 00576 unsigned isooutdrop:1; 00577 unsigned eopframe:1; 00578 unsigned intokenrx:1; 00579 unsigned epmismatch:1; 00580 unsigned inepint:1; 00581 unsigned outepintr:1; 00582 unsigned incomplisoin:1; 00583 unsigned incomplisoout:1; 00584 unsigned reserved22_23:2; 00585 unsigned portintr:1; 00586 unsigned hcintr:1; 00587 unsigned ptxfempty:1; 00588 unsigned lpmtranrcvd:1; 00589 unsigned conidstschng:1; 00590 unsigned disconnect:1; 00591 unsigned sessreqintr:1; 00592 unsigned wkupintr:1; 00593 } b; 00594 } gintsts_data_t; 00595 00601 typedef union device_grxsts_data { 00603 uint32_t d32; 00605 struct { 00606 unsigned epnum:4; 00607 unsigned bcnt:11; 00608 unsigned dpid:2; 00609 00610 #define DWC_STS_DATA_UPDT 0x2 // OUT Data Packet 00611 #define DWC_STS_XFER_COMP 0x3 // OUT Data Transfer Complete 00612 00613 #define DWC_DSTS_GOUT_NAK 0x1 // Global OUT NAK 00614 #define DWC_DSTS_SETUP_COMP 0x4 // Setup Phase Complete 00615 #define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet 00616 unsigned pktsts:4; 00617 unsigned fn:4; 00618 unsigned reserved:7; 00619 } b; 00620 } device_grxsts_data_t; 00621 00627 typedef union host_grxsts_data { 00629 uint32_t d32; 00631 struct { 00632 unsigned chnum:4; 00633 unsigned bcnt:11; 00634 unsigned dpid:2; 00635 00636 unsigned pktsts:4; 00637 #define DWC_GRXSTS_PKTSTS_IN 0x2 00638 #define DWC_GRXSTS_PKTSTS_IN_XFER_COMP 0x3 00639 #define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5 00640 #define DWC_GRXSTS_PKTSTS_CH_HALTED 0x7 00641 00642 unsigned reserved:11; 00643 } b; 00644 } host_grxsts_data_t; 00645 00651 typedef union fifosize_data { 00653 uint32_t d32; 00655 struct { 00656 unsigned startaddr:16; 00657 unsigned depth:16; 00658 } b; 00659 } fifosize_data_t; 00660 00667 typedef union gnptxsts_data { 00669 uint32_t d32; 00671 struct { 00672 unsigned nptxfspcavail:16; 00673 unsigned nptxqspcavail:8; 00684 unsigned nptxqtop_terminate:1; 00685 unsigned nptxqtop_token:2; 00686 unsigned nptxqtop_chnep:4; 00687 unsigned reserved:1; 00688 } b; 00689 } gnptxsts_data_t; 00690 00697 typedef union dtxfsts_data { 00699 uint32_t d32; 00701 struct { 00702 unsigned txfspcavail:16; 00703 unsigned reserved:16; 00704 } b; 00705 } dtxfsts_data_t; 00706 00712 typedef union gi2cctl_data { 00714 uint32_t d32; 00716 struct { 00717 unsigned rwdata:8; 00718 unsigned regaddr:8; 00719 unsigned addr:7; 00720 unsigned i2cen:1; 00721 unsigned ack:1; 00722 unsigned i2csuspctl:1; 00723 unsigned i2cdevaddr:2; 00724 unsigned reserved:2; 00725 unsigned rw:1; 00726 unsigned bsydne:1; 00727 } b; 00728 } gi2cctl_data_t; 00729 00735 typedef union hwcfg1_data { 00737 uint32_t d32; 00739 struct { 00740 unsigned ep_dir0:2; 00741 unsigned ep_dir1:2; 00742 unsigned ep_dir2:2; 00743 unsigned ep_dir3:2; 00744 unsigned ep_dir4:2; 00745 unsigned ep_dir5:2; 00746 unsigned ep_dir6:2; 00747 unsigned ep_dir7:2; 00748 unsigned ep_dir8:2; 00749 unsigned ep_dir9:2; 00750 unsigned ep_dir10:2; 00751 unsigned ep_dir11:2; 00752 unsigned ep_dir12:2; 00753 unsigned ep_dir13:2; 00754 unsigned ep_dir14:2; 00755 unsigned ep_dir15:2; 00756 } b; 00757 } hwcfg1_data_t; 00758 00764 typedef union hwcfg2_data { 00766 uint32_t d32; 00768 struct { 00769 /* GHWCFG2 */ 00770 unsigned op_mode:3; 00771 #define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0 00772 #define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1 00773 #define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2 00774 #define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3 00775 #define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4 00776 #define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5 00777 #define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6 00778 00779 unsigned architecture:2; 00780 unsigned point2point:1; 00781 unsigned hs_phy_type:2; 00782 #define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0 00783 #define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1 00784 #define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2 00785 #define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3 00786 00787 unsigned fs_phy_type:2; 00788 unsigned num_dev_ep:4; 00789 unsigned num_host_chan:4; 00790 unsigned perio_ep_supported:1; 00791 unsigned dynamic_fifo:1; 00792 unsigned multi_proc_int:1; 00793 unsigned reserved21:1; 00794 unsigned nonperio_tx_q_depth:2; 00795 unsigned host_perio_tx_q_depth:2; 00796 unsigned dev_token_q_depth:5; 00797 unsigned reserved31:1; 00798 } b; 00799 } hwcfg2_data_t; 00800 00806 typedef union hwcfg3_data { 00808 uint32_t d32; 00810 struct { 00811 /* GHWCFG3 */ 00812 unsigned xfer_size_cntr_width:4; 00813 unsigned packet_size_cntr_width:3; 00814 unsigned otg_func:1; 00815 unsigned i2c:1; 00816 unsigned vendor_ctrl_if:1; 00817 unsigned optional_features:1; 00818 unsigned synch_reset_type:1; 00819 unsigned otg_enable_ic_usb:1; 00820 unsigned otg_enable_hsic:1; 00821 unsigned reserved14:1; 00822 unsigned otg_lpm_en:1; 00823 unsigned dfifo_depth:16; 00824 } b; 00825 } hwcfg3_data_t; 00826 00832 typedef union hwcfg4_data { 00834 uint32_t d32; 00836 struct { 00837 unsigned num_dev_perio_in_ep:4; 00838 unsigned power_optimiz:1; 00839 unsigned min_ahb_freq:9; 00840 unsigned utmi_phy_data_width:2; 00841 unsigned num_dev_mode_ctrl_ep:4; 00842 unsigned iddig_filt_en:1; 00843 unsigned vbus_valid_filt_en:1; 00844 unsigned a_valid_filt_en:1; 00845 unsigned b_valid_filt_en:1; 00846 unsigned session_end_filt_en:1; 00847 unsigned ded_fifo_en:1; 00848 unsigned num_in_eps:4; 00849 unsigned desc_dma:1; 00850 unsigned desc_dma_dyn:1; 00851 } b; 00852 } hwcfg4_data_t; 00853 00855 // Device Registers 00865 typedef struct dwc_otg_dev_global_regs { 00867 volatile uint32_t dcfg; 00869 volatile uint32_t dctl; 00871 volatile uint32_t dsts; 00873 uint32_t unused; 00876 volatile uint32_t diepmsk; 00879 volatile uint32_t doepmsk; 00881 volatile uint32_t daint; 00884 volatile uint32_t daintmsk; 00887 volatile uint32_t dtknqr1; 00890 volatile uint32_t dtknqr2; 00892 volatile uint32_t dvbusdis; 00894 volatile uint32_t dvbuspulse; 00898 volatile uint32_t dtknqr3_dthrctl; 00902 volatile uint32_t dtknqr4_fifoemptymsk; 00905 volatile uint32_t deachint; 00908 volatile uint32_t deachintmsk; 00911 volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS]; 00914 volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS]; 00915 } dwc_otg_device_global_regs_t; 00916 00923 typedef union dcfg_data { 00925 uint32_t d32; 00927 struct { 00929 unsigned devspd:2; 00931 unsigned nzstsouthshk:1; 00932 #define DWC_DCFG_SEND_STALL 1 00933 00934 unsigned reserved3:1; 00936 unsigned devaddr:7; 00938 unsigned perfrint:2; 00939 #define DWC_DCFG_FRAME_INTERVAL_80 0 00940 #define DWC_DCFG_FRAME_INTERVAL_85 1 00941 #define DWC_DCFG_FRAME_INTERVAL_90 2 00942 #define DWC_DCFG_FRAME_INTERVAL_95 3 00943 00944 unsigned reserved13_17:5; 00946 unsigned epmscnt:5; 00948 unsigned descdma:1; 00949 } b; 00950 } dcfg_data_t; 00951 00957 typedef union dctl_data { 00959 uint32_t d32; 00961 struct { 00963 unsigned rmtwkupsig:1; 00965 unsigned sftdiscon:1; 00967 unsigned gnpinnaksts:1; 00969 unsigned goutnaksts:1; 00971 unsigned tstctl:3; 00973 unsigned sgnpinnak:1; 00975 unsigned cgnpinnak:1; 00977 unsigned sgoutnak:1; 00979 unsigned cgoutnak:1; 00980 00982 unsigned pwronprgdone:1; 00984 unsigned gcontbna:1; 00986 unsigned gmc:2; 00988 unsigned ifrmnum:1; 00990 unsigned nakonbble:1; 00991 00992 unsigned reserved17_31:15; 00993 } b; 00994 } dctl_data_t; 00995 01001 typedef union dsts_data { 01003 uint32_t d32; 01005 struct { 01007 unsigned suspsts:1; 01009 unsigned enumspd:2; 01010 #define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 01011 #define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 01012 #define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2 01013 #define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3 01014 01015 unsigned errticerr:1; 01016 unsigned reserved4_7:4; 01018 unsigned soffn:14; 01019 unsigned reserved22_31:10; 01020 } b; 01021 } dsts_data_t; 01022 01030 typedef union diepint_data { 01032 uint32_t d32; 01034 struct { 01036 unsigned xfercompl:1; 01038 unsigned epdisabled:1; 01040 unsigned ahberr:1; 01042 unsigned timeout:1; 01044 unsigned intktxfemp:1; 01046 unsigned intknepmis:1; 01048 unsigned inepnakeff:1; 01050 unsigned emptyintr:1; 01051 01052 unsigned txfifoundrn:1; 01053 01055 unsigned bna:1; 01056 01057 unsigned reserved10_12:3; 01059 unsigned nak:1; 01060 01061 unsigned reserved14_31:18; 01062 } b; 01063 } diepint_data_t; 01064 01069 typedef union diepint_data diepmsk_data_t; 01070 01078 typedef union doepint_data { 01080 uint32_t d32; 01082 struct { 01084 unsigned xfercompl:1; 01086 unsigned epdisabled:1; 01088 unsigned ahberr:1; 01090 unsigned setup:1; 01092 unsigned outtknepdis:1; 01093 01094 unsigned stsphsercvd:1; 01096 unsigned back2backsetup:1; 01097 01098 unsigned reserved7:1; 01100 unsigned outpkterr:1; 01102 unsigned bna:1; 01103 01104 unsigned reserved10:1; 01106 unsigned pktdrpsts:1; 01108 unsigned babble:1; 01110 unsigned nak:1; 01112 unsigned nyet:1; 01113 01114 unsigned reserved15_31:17; 01115 } b; 01116 } doepint_data_t; 01117 01122 typedef union doepint_data doepmsk_data_t; 01123 01130 typedef union daint_data { 01132 uint32_t d32; 01134 struct { 01136 unsigned in:16; 01138 unsigned out:16; 01139 } ep; 01140 struct { 01142 unsigned inep0:1; 01143 unsigned inep1:1; 01144 unsigned inep2:1; 01145 unsigned inep3:1; 01146 unsigned inep4:1; 01147 unsigned inep5:1; 01148 unsigned inep6:1; 01149 unsigned inep7:1; 01150 unsigned inep8:1; 01151 unsigned inep9:1; 01152 unsigned inep10:1; 01153 unsigned inep11:1; 01154 unsigned inep12:1; 01155 unsigned inep13:1; 01156 unsigned inep14:1; 01157 unsigned inep15:1; 01159 unsigned outep0:1; 01160 unsigned outep1:1; 01161 unsigned outep2:1; 01162 unsigned outep3:1; 01163 unsigned outep4:1; 01164 unsigned outep5:1; 01165 unsigned outep6:1; 01166 unsigned outep7:1; 01167 unsigned outep8:1; 01168 unsigned outep9:1; 01169 unsigned outep10:1; 01170 unsigned outep11:1; 01171 unsigned outep12:1; 01172 unsigned outep13:1; 01173 unsigned outep14:1; 01174 unsigned outep15:1; 01175 } b; 01176 } daint_data_t; 01177 01184 typedef union dtknq1_data { 01186 uint32_t d32; 01188 struct { 01190 unsigned intknwptr:5; 01192 unsigned reserved05_06:2; 01194 unsigned wrap_bit:1; 01196 unsigned epnums0_5:24; 01197 } b; 01198 } dtknq1_data_t; 01199 01205 typedef union dthrctl_data { 01207 uint32_t d32; 01209 struct { 01211 unsigned non_iso_thr_en:1; 01213 unsigned iso_thr_en:1; 01215 unsigned tx_thr_len:9; 01217 unsigned ahb_thr_ratio:2; 01219 unsigned reserved13_15:3; 01221 unsigned rx_thr_en:1; 01223 unsigned rx_thr_len:9; 01225 unsigned reserved26_31:6; 01226 } b; 01227 } dthrctl_data_t; 01228 01239 typedef struct dwc_otg_dev_in_ep_regs { 01242 volatile uint32_t diepctl; 01244 uint32_t reserved04; 01247 volatile uint32_t diepint; 01249 uint32_t reserved0C; 01252 volatile uint32_t dieptsiz; 01255 volatile uint32_t diepdma; 01258 volatile uint32_t dtxfsts; 01261 volatile uint32_t diepdmab; 01262 } dwc_otg_dev_in_ep_regs_t; 01263 01274 typedef struct dwc_otg_dev_out_ep_regs { 01277 volatile uint32_t doepctl; 01280 volatile uint32_t doepfn; 01283 volatile uint32_t doepint; 01285 uint32_t reserved0C; 01288 volatile uint32_t doeptsiz; 01291 volatile uint32_t doepdma; 01293 uint32_t unused; 01296 uint32_t doepdmab; 01297 } dwc_otg_dev_out_ep_regs_t; 01298 01304 typedef union depctl_data { 01306 uint32_t d32; 01308 struct { 01316 unsigned mps:11; 01317 #define DWC_DEP0CTL_MPS_64 0 01318 #define DWC_DEP0CTL_MPS_32 1 01319 #define DWC_DEP0CTL_MPS_16 2 01320 #define DWC_DEP0CTL_MPS_8 3 01321 01325 unsigned nextep:4; 01326 01328 unsigned usbactep:1; 01329 01344 unsigned dpid:1; 01345 01347 unsigned naksts:1; 01348 01354 unsigned eptype:2; 01355 01359 unsigned snp:1; 01360 01362 unsigned stall:1; 01363 01367 unsigned txfnum:4; 01368 01370 unsigned cnak:1; 01372 unsigned snak:1; 01381 unsigned setd0pid:1; 01389 unsigned setd1pid:1; 01390 01392 unsigned epdis:1; 01394 unsigned epena:1; 01395 } b; 01396 } depctl_data_t; 01397 01403 typedef union deptsiz_data { 01405 uint32_t d32; 01407 struct { 01409 unsigned xfersize:19; 01411 unsigned pktcnt:10; 01413 unsigned mc:2; 01414 unsigned reserved:1; 01415 } b; 01416 } deptsiz_data_t; 01417 01423 typedef union deptsiz0_data { 01425 uint32_t d32; 01427 struct { 01429 unsigned xfersize:7; 01431 unsigned reserved7_18:12; 01433 unsigned pktcnt:1; 01435 unsigned reserved20_28:9; 01437 unsigned supcnt:2; 01438 unsigned reserved31; 01439 } b; 01440 } deptsiz0_data_t; 01441 01443 // DMA Descriptor Specific Structures 01444 // 01445 01448 #define BS_HOST_READY 0x0 01449 #define BS_DMA_BUSY 0x1 01450 #define BS_DMA_DONE 0x2 01451 #define BS_HOST_BUSY 0x3 01452 01455 #define RTS_SUCCESS 0x0 01456 #define RTS_BUFFLUSH 0x1 01457 #define RTS_RESERVED 0x2 01458 #define RTS_BUFERR 0x3 01459 01466 typedef union dev_dma_desc_sts { 01468 uint32_t d32; 01470 struct { 01472 unsigned bytes:16; 01473 01474 unsigned reserved16_22:7; 01476 unsigned mtrf:1; 01478 unsigned sr:1; 01480 unsigned ioc:1; 01482 unsigned sp:1; 01484 unsigned l:1; 01486 unsigned sts:2; 01488 unsigned bs:2; 01489 } b; 01490 01491 #ifdef DWC_EN_ISOC 01492 01493 struct { 01495 unsigned rxbytes:11; 01496 01497 unsigned reserved11:1; 01499 unsigned framenum:11; 01501 unsigned pid:2; 01503 unsigned ioc:1; 01505 unsigned sp:1; 01507 unsigned l:1; 01509 unsigned rxsts:2; 01511 unsigned bs:2; 01512 } b_iso_out; 01513 01515 struct { 01517 unsigned txbytes:12; 01519 unsigned framenum:11; 01521 unsigned pid:2; 01523 unsigned ioc:1; 01525 unsigned sp:1; 01527 unsigned l:1; 01529 unsigned txsts:2; 01531 unsigned bs:2; 01532 } b_iso_in; 01533 #endif /* DWC_EN_ISOC */ 01534 } dev_dma_desc_sts_t; 01535 01542 typedef struct dwc_otg_dev_dma_desc { 01544 dev_dma_desc_sts_t status; 01546 uint32_t buf; 01547 } dwc_otg_dev_dma_desc_t; 01548 01554 typedef struct dwc_otg_dev_if { 01558 dwc_otg_device_global_regs_t *dev_global_regs; 01559 #define DWC_DEV_GLOBAL_REG_OFFSET 0x800 01560 01564 dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS]; 01565 #define DWC_DEV_IN_EP_REG_OFFSET 0x900 01566 #define DWC_EP_REG_OFFSET 0x20 01567 01569 dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS]; 01570 #define DWC_DEV_OUT_EP_REG_OFFSET 0xB00 01571 01572 /* Device configuration information */ 01573 uint8_t speed; 01574 uint8_t num_in_eps; 01575 uint8_t num_out_eps; 01578 uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS]; 01579 01581 uint16_t tx_fifo_size[MAX_TX_FIFOS]; 01582 01584 uint16_t rx_thr_en; 01585 uint16_t iso_tx_thr_en; 01586 uint16_t non_iso_tx_thr_en; 01587 01588 uint16_t rx_thr_length; 01589 uint16_t tx_thr_length; 01590 01597 dwc_dma_t dma_setup_desc_addr[2]; 01598 dwc_otg_dev_dma_desc_t *setup_desc_addr[2]; 01599 01601 dwc_otg_dev_dma_desc_t *psetup; 01602 01604 uint32_t setup_desc_index; 01605 01607 dwc_dma_t dma_in_desc_addr; 01608 dwc_otg_dev_dma_desc_t *in_desc_addr; 01609 01611 dwc_dma_t dma_out_desc_addr; 01612 dwc_otg_dev_dma_desc_t *out_desc_addr; 01613 01615 uint32_t spd; 01616 01617 } dwc_otg_dev_if_t; 01618 01620 // Host Mode Register Structures 01621 // 01627 typedef struct dwc_otg_host_global_regs { 01629 volatile uint32_t hcfg; 01631 volatile uint32_t hfir; 01633 volatile uint32_t hfnum; 01635 uint32_t reserved40C; 01637 volatile uint32_t hptxsts; 01639 volatile uint32_t haint; 01641 volatile uint32_t haintmsk; 01643 volatile uint32_t hflbaddr; 01644 } dwc_otg_host_global_regs_t; 01645 01646 01652 typedef union hcfg_data 01653 { 01655 uint32_t d32; 01656 01658 struct 01659 { 01661 unsigned fslspclksel:2; 01662 #define DWC_HCFG_30_60_MHZ 0 01663 #define DWC_HCFG_48_MHZ 1 01664 #define DWC_HCFG_6_MHZ 2 01665 01667 unsigned fslssupp:1; 01668 unsigned reserved3_22 : 20; 01670 unsigned descdma : 1; 01672 unsigned frlisten: 2; 01674 unsigned perschedena: 1; 01676 unsigned perschedstat: 1; 01677 } b; 01678 } hcfg_data_t; 01679 01684 typedef union hfir_data { 01686 uint32_t d32; 01687 01689 struct { 01690 unsigned frint:16; 01691 unsigned reserved:16; 01692 } b; 01693 } hfir_data_t; 01694 01699 typedef union hfnum_data { 01701 uint32_t d32; 01702 01704 struct { 01705 unsigned frnum:16; 01706 #define DWC_HFNUM_MAX_FRNUM 0x3FFF 01707 unsigned frrem:16; 01708 } b; 01709 } hfnum_data_t; 01710 01711 typedef union hptxsts_data { 01713 uint32_t d32; 01714 01716 struct { 01717 unsigned ptxfspcavail:16; 01718 unsigned ptxqspcavail:8; 01728 unsigned ptxqtop_terminate:1; 01729 unsigned ptxqtop_token:2; 01730 unsigned ptxqtop_chnum:4; 01731 unsigned ptxqtop_odd:1; 01732 } b; 01733 } hptxsts_data_t; 01734 01741 typedef union hprt0_data { 01743 uint32_t d32; 01745 struct { 01746 unsigned prtconnsts:1; 01747 unsigned prtconndet:1; 01748 unsigned prtena:1; 01749 unsigned prtenchng:1; 01750 unsigned prtovrcurract:1; 01751 unsigned prtovrcurrchng:1; 01752 unsigned prtres:1; 01753 unsigned prtsusp:1; 01754 unsigned prtrst:1; 01755 unsigned reserved9:1; 01756 unsigned prtlnsts:2; 01757 unsigned prtpwr:1; 01758 unsigned prttstctl:4; 01759 unsigned prtspd:2; 01760 #define DWC_HPRT0_PRTSPD_HIGH_SPEED 0 01761 #define DWC_HPRT0_PRTSPD_FULL_SPEED 1 01762 #define DWC_HPRT0_PRTSPD_LOW_SPEED 2 01763 unsigned reserved19_31:13; 01764 } b; 01765 } hprt0_data_t; 01766 01771 typedef union haint_data { 01773 uint32_t d32; 01775 struct { 01776 unsigned ch0:1; 01777 unsigned ch1:1; 01778 unsigned ch2:1; 01779 unsigned ch3:1; 01780 unsigned ch4:1; 01781 unsigned ch5:1; 01782 unsigned ch6:1; 01783 unsigned ch7:1; 01784 unsigned ch8:1; 01785 unsigned ch9:1; 01786 unsigned ch10:1; 01787 unsigned ch11:1; 01788 unsigned ch12:1; 01789 unsigned ch13:1; 01790 unsigned ch14:1; 01791 unsigned ch15:1; 01792 unsigned reserved:16; 01793 } b; 01794 01795 struct { 01796 unsigned chint:16; 01797 unsigned reserved:16; 01798 } b2; 01799 } haint_data_t; 01800 01805 typedef union haintmsk_data { 01807 uint32_t d32; 01809 struct { 01810 unsigned ch0:1; 01811 unsigned ch1:1; 01812 unsigned ch2:1; 01813 unsigned ch3:1; 01814 unsigned ch4:1; 01815 unsigned ch5:1; 01816 unsigned ch6:1; 01817 unsigned ch7:1; 01818 unsigned ch8:1; 01819 unsigned ch9:1; 01820 unsigned ch10:1; 01821 unsigned ch11:1; 01822 unsigned ch12:1; 01823 unsigned ch13:1; 01824 unsigned ch14:1; 01825 unsigned ch15:1; 01826 unsigned reserved:16; 01827 } b; 01828 01829 struct { 01830 unsigned chint:16; 01831 unsigned reserved:16; 01832 } b2; 01833 } haintmsk_data_t; 01834 01838 typedef struct dwc_otg_hc_regs 01839 { 01841 volatile uint32_t hcchar; 01843 volatile uint32_t hcsplt; 01845 volatile uint32_t hcint; 01847 volatile uint32_t hcintmsk; 01849 volatile uint32_t hctsiz; 01851 volatile uint32_t hcdma; 01852 volatile uint32_t reserved; 01854 volatile uint32_t hcdmab; 01855 } dwc_otg_hc_regs_t; 01856 01863 typedef union hcchar_data { 01865 uint32_t d32; 01866 01868 struct { 01870 unsigned mps:11; 01871 01873 unsigned epnum:4; 01874 01876 unsigned epdir:1; 01877 01878 unsigned reserved:1; 01879 01881 unsigned lspddev:1; 01882 01884 unsigned eptype:2; 01885 01887 unsigned multicnt:2; 01888 01890 unsigned devaddr:7; 01891 01896 unsigned oddfrm:1; 01897 01899 unsigned chdis:1; 01900 01902 unsigned chen:1; 01903 } b; 01904 } hcchar_data_t; 01905 01906 typedef union hcsplt_data { 01908 uint32_t d32; 01909 01911 struct { 01913 unsigned prtaddr:7; 01914 01916 unsigned hubaddr:7; 01917 01919 unsigned xactpos:2; 01920 #define DWC_HCSPLIT_XACTPOS_MID 0 01921 #define DWC_HCSPLIT_XACTPOS_END 1 01922 #define DWC_HCSPLIT_XACTPOS_BEGIN 2 01923 #define DWC_HCSPLIT_XACTPOS_ALL 3 01924 01926 unsigned compsplt:1; 01927 01929 unsigned reserved:14; 01930 01932 unsigned spltena:1; 01933 } b; 01934 } hcsplt_data_t; 01935 01940 typedef union hcint_data 01941 { 01943 uint32_t d32; 01945 struct 01946 { 01948 unsigned xfercomp:1; 01950 unsigned chhltd:1; 01952 unsigned ahberr:1; 01954 unsigned stall:1; 01956 unsigned nak:1; 01958 unsigned ack:1; 01960 unsigned nyet:1; 01962 unsigned xacterr:1; 01964 unsigned bblerr:1; 01966 unsigned frmovrun:1; 01968 unsigned datatglerr:1; 01970 unsigned bna : 1; 01972 unsigned xcs_xact : 1; 01974 unsigned frm_list_roll : 1; 01976 unsigned reserved14_31 : 18; 01977 } b; 01978 } hcint_data_t; 01979 01986 typedef union hcintmsk_data 01987 { 01989 uint32_t d32; 01990 01992 struct 01993 { 01994 unsigned xfercompl : 1; 01995 unsigned chhltd : 1; 01996 unsigned ahberr : 1; 01997 unsigned stall : 1; 01998 unsigned nak : 1; 01999 unsigned ack : 1; 02000 unsigned nyet : 1; 02001 unsigned xacterr : 1; 02002 unsigned bblerr : 1; 02003 unsigned frmovrun : 1; 02004 unsigned datatglerr : 1; 02005 unsigned bna : 1; 02006 unsigned xcs_xact : 1; 02007 unsigned frm_list_roll : 1; 02008 unsigned reserved14_31 : 18; 02009 } b; 02010 } hcintmsk_data_t; 02011 02019 typedef union hctsiz_data 02020 { 02022 uint32_t d32; 02023 02025 struct 02026 { 02028 unsigned xfersize:19; 02029 02031 unsigned pktcnt:10; 02032 02040 unsigned pid:2; 02041 #define DWC_HCTSIZ_DATA0 0 02042 #define DWC_HCTSIZ_DATA1 2 02043 #define DWC_HCTSIZ_DATA2 1 02044 #define DWC_HCTSIZ_MDATA 3 02045 #define DWC_HCTSIZ_SETUP 3 02046 02048 unsigned dopng:1; 02049 } b; 02050 02052 struct 02053 { 02055 unsigned schinfo : 8; 02056 02062 unsigned ntd : 8; 02063 02065 unsigned reserved16_28 : 13; 02066 02074 unsigned pid : 2; 02075 02077 unsigned dopng : 1; 02078 } b_ddma; 02079 } hctsiz_data_t; 02080 02081 02086 typedef union hcdma_data 02087 { 02089 uint32_t d32; 02091 struct 02092 { 02093 unsigned reserved0_2 : 3; 02095 unsigned ctd : 8; 02097 unsigned dma_addr : 21; 02098 } b; 02099 } hcdma_data_t; 02100 02106 typedef union host_dma_desc_sts 02107 { 02109 uint32_t d32; 02112 /* for non-isochronous */ 02113 struct { 02115 unsigned n_bytes : 17; 02117 unsigned qtd_offset : 6; 02122 unsigned a_qtd : 1; 02127 unsigned sup : 1; 02129 unsigned ioc : 1; 02131 unsigned eol : 1; 02132 unsigned reserved27 : 1; 02134 unsigned sts : 2; 02135 #define DMA_DESC_STS_PKTERR 1 02136 unsigned reserved30 : 1; 02138 unsigned a : 1; 02139 } b; 02140 /* for isochronous */ 02141 struct { 02143 unsigned n_bytes : 12; 02144 unsigned reserved12_24 : 13; 02146 unsigned ioc : 1; 02147 unsigned reserved26_27 : 2; 02149 unsigned sts : 2; 02150 unsigned reserved30 : 1; 02152 unsigned a : 1; 02153 } b_isoc; 02154 } host_dma_desc_sts_t; 02155 02156 #define MAX_DMA_DESC_SIZE 131071 02157 #define MAX_DMA_DESC_NUM_GENERIC 64 02158 #define MAX_DMA_DESC_NUM_HS_ISOC 256 02159 #define MAX_FRLIST_EN_NUM 64 02160 02166 typedef struct dwc_otg_host_dma_desc 02167 { 02169 host_dma_desc_sts_t status; 02171 uint32_t buf; 02172 } dwc_otg_host_dma_desc_t; 02173 02181 typedef struct dwc_otg_host_if { 02183 dwc_otg_host_global_regs_t *host_global_regs; 02184 #define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400 02185 02187 volatile uint32_t *hprt0; 02188 #define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440 02189 02191 dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS]; 02192 #define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500 02193 #define DWC_OTG_CHAN_REGS_OFFSET 0x20 02194 02195 /* Host configuration information */ 02197 uint8_t num_host_channels; 02199 uint8_t perio_eps_supported; 02201 uint16_t perio_tx_fifo_size; 02202 02203 } dwc_otg_host_if_t; 02204 02210 typedef union pcgcctl_data { 02212 uint32_t d32; 02213 02215 struct { 02217 unsigned stoppclk:1; 02219 unsigned gatehclk:1; 02221 unsigned pwrclmp:1; 02223 unsigned rstpdwnmodule:1; 02225 unsigned physuspended:1; 02227 unsigned enbl_sleep_gating:1; 02229 unsigned phy_in_sleep:1; 02231 unsigned deep_sleep:1; 02232 02233 unsigned reserved31_8:24; 02234 } b; 02235 } pcgcctl_data_t; 02236 02237 #endif
1.4.7