#include <dwc_otg_regs.h>
Data Fields | |
| uint32_t | d32 |
| raw register data | |
| struct { | |
| unsigned csftrst:1 | |
| Core Soft Reset (CSftRst) (Device and Host). | |
| unsigned hsftrst:1 | |
| Hclk Soft Reset. | |
| unsigned hstfrm:1 | |
| Host Frame Counter Reset (Host Only) . | |
| unsigned intknqflsh:1 | |
| In Token Sequence Learning Queue Flush (INTknQFlsh) (Device Only). | |
| unsigned rxfflsh:1 | |
| RxFIFO Flush (RxFFlsh) (Device and Host). | |
| unsigned txfflsh:1 | |
| TxFIFO Flush (TxFFlsh) (Device and Host). | |
| unsigned txfnum:5 | |
| TxFIFO Number (TxFNum) (Device and Host). | |
| unsigned reserved11_29:19 | |
| Reserved. | |
| unsigned dmareq:1 | |
| DMA Request Signal. | |
| unsigned ahbidle:1 | |
| AHB Master Idle. | |
| } | b |
| register bits | |
Set/clear the bits using the bit fields then write the d32 value to the register.
Definition at line 388 of file dwc_otg_regs.h.
| unsigned grstctl_data::csftrst |
Core Soft Reset (CSftRst) (Device and Host).
The application can flush the control logic in the entire core using this bit. This bit resets the pipelines in the AHB Clock domain as well as the PHY Clock domain.
The state machines are reset to an IDLE state, the control bits in the CSRs are cleared, all the transmit FIFOs and the receive FIFO are flushed.
The status mask bits that control the generation of the interrupt, are cleared, to clear the interrupt. The interrupt status bits are not cleared, so the application can get the status of any events that occurred in the core after it has set this bit.
Any transactions on the AHB are terminated as soon as possible following the protocol. Any transactions on the USB are terminated immediately.
The configuration settings in the CSRs are unchanged, so the software doesn't have to reprogram these registers (Device Configuration/Host Configuration/Core System Configuration/Core PHY Configuration).
The application can write to this bit, any time it wants to reset the core. This is a self clearing bit and the core clears this bit after all the necessary logic is reset in the core, which may take several clocks, depending on the current state of the core.
Definition at line 428 of file dwc_otg_regs.h.
| unsigned grstctl_data::hsftrst |
Hclk Soft Reset.
The application uses this bit to reset the control logic in the AHB clock domain. Only AHB clock domain pipelines are reset.
Definition at line 435 of file dwc_otg_regs.h.
| unsigned grstctl_data::hstfrm |
Host Frame Counter Reset (Host Only)
.
The application can reset the (micro)frame number counter inside the core, using this bit. When the (micro)frame counter is reset, the subsequent SOF sent out by the core, will have a (micro)frame number of 0.
Definition at line 444 of file dwc_otg_regs.h.
| unsigned grstctl_data::rxfflsh |
RxFIFO Flush (RxFFlsh) (Device and Host).
The application can flush the entire Receive FIFO using this bit.
The application must first ensure that the core is not in the middle of a transaction.
The application should write into this bit, only after making sure that neither the DMA engine is reading from the RxFIFO nor the MAC is writing the data in to the FIFO.
The application should wait until the bit is cleared before performing any other operations. This bit will takes 8 clocks (slowest of PHY or AHB clock) to clear.
Definition at line 463 of file dwc_otg_regs.h.
| unsigned grstctl_data::txfflsh |
TxFIFO Flush (TxFFlsh) (Device and Host).
This bit is used to selectively flush a single or all transmit FIFOs. The application must first ensure that the core is not in the middle of a transaction.
The application should write into this bit, only after making sure that neither the DMA engine is writing into the TxFIFO nor the MAC is reading the data out of the FIFO.
The application should wait until the core clears this bit, before performing any operations. This bit will takes 8 clocks (slowest of PHY or AHB clock) to clear.
Definition at line 478 of file dwc_otg_regs.h.
| unsigned grstctl_data::txfnum |
TxFIFO Number (TxFNum) (Device and Host).
This is the FIFO number which needs to be flushed, using the TxFIFO Flush bit. This field should not be changed until the TxFIFO Flush bit is cleared by the core.
Definition at line 495 of file dwc_otg_regs.h.
| unsigned grstctl_data::dmareq |
DMA Request Signal.
Indicated DMA request is in probress. Used for debug purpose.
Definition at line 500 of file dwc_otg_regs.h.
| unsigned grstctl_data::ahbidle |
AHB Master Idle.
Indicates the AHB Master State Machine is in IDLE condition.
Definition at line 503 of file dwc_otg_regs.h.
1.4.7