glpmctl_data Union Reference

This union represents the bit fields of the Core LPM Configuration Register (GLPMCFG). More...

#include <dwc_otg_regs.h>


Data Fields

uint32_t d32
 raw register data
struct {
   unsigned   lpm_cap_en:1
 LPM-Capable (LPMCap) (Device and Host) The application uses this bit to control the DWC_otg core LPM capabilities.
   unsigned   appl_resp:1
 LPM response programmed by application (AppL1Res) (Device) Handshake response to LPM token pre-programmed by device application software.
   unsigned   hird:4
 Host Initiated Resume Duration (HIRD) (Device and Host) In Host mode this field indicates the value of HIRD to be sent in an LPM transaction.
   unsigned   rem_wkup_en:1
 RemoteWakeEnable (bRemoteWake) (Device and Host) In Host mode this bit indicates the value of remote wake up to be sent in wIndex field of LPM transaction.
   unsigned   en_utmi_sleep:1
 Enable utmi_sleep_n (EnblSlpM) (Device and Host) The application uses this bit to control the utmi_sleep_n assertion to the PHY when in L1 state.
   unsigned   hird_thres:5
 HIRD Threshold (HIRD_Thres) (Device and Host).
   unsigned   lpm_resp:2
 LPM Response (CoreL1Res) (Device and Host) In Host mode this bit contains handsake response to LPM transaction.
   unsigned   prt_sleep_sts:1
 Port Sleep Status (SlpSts) (Device and Host) This bit is set as long as a Sleep condition is present on the USB bus.
   unsigned   sleep_state_resumeok:1
 Sleep State Resume OK (L1ResumeOK) (Device and Host) Indicates that the application or host can start resume from Sleep state.
   unsigned   lpm_chan_index:4
 LPM channel Index (LPM_Chnl_Indx) (Host) The channel number on which the LPM transaction has to be applied while sending an LPM transaction to the local device.
   unsigned   retry_count:3
 LPM Retry Count (LPM_Retry_Cnt) (Host) Number host retries that would be performed if the device response was not valid response.
   unsigned   send_lpm:1
 Send LPM Transaction (SndLPM) (Host) When set by application software, an LPM transaction containing two tokens is sent.
   unsigned   retry_count_sts:3
 LPM Retry status (LPM_RetryCnt_Sts) (Host) Number of LPM Host Retries still remaining to be transmitted for the current LPM sequence.
   unsigned   reserved28_29:2
   unsigned   hsic_connect:1
 In host mode once this bit is set, the host configures to drive the HSIC Idle state on the bus.
   unsigned   inv_sel_hsic:1
 This bit overrides and functionally inverts the if_select_hsic input port signal.
b
 register bits


Detailed Description

This union represents the bit fields of the Core LPM Configuration Register (GLPMCFG).

Set the bits using bit fields then write the d32 value to the register.

Definition at line 283 of file dwc_otg_regs.h.


Field Documentation

unsigned glpmctl_data::hird

Host Initiated Resume Duration (HIRD) (Device and Host) In Host mode this field indicates the value of HIRD to be sent in an LPM transaction.

In Device mode this field is updated with the Received LPM Token HIRD bmAttribute when an ACK/NYET/STALL response is sent to an LPM transaction.

Definition at line 306 of file dwc_otg_regs.h.

unsigned glpmctl_data::rem_wkup_en

RemoteWakeEnable (bRemoteWake) (Device and Host) In Host mode this bit indicates the value of remote wake up to be sent in wIndex field of LPM transaction.

In Device mode this field is updated with the Received LPM Token bRemoteWake bmAttribute when an ACK/NYET/STALL response is sent to an LPM transaction.

Definition at line 315 of file dwc_otg_regs.h.

unsigned glpmctl_data::lpm_resp

LPM Response (CoreL1Res) (Device and Host) In Host mode this bit contains handsake response to LPM transaction.

In Device mode the response of the core to LPM transaction received is reflected in these two bits.

Definition at line 334 of file dwc_otg_regs.h.

unsigned glpmctl_data::hsic_connect

In host mode once this bit is set, the host configures to drive the HSIC Idle state on the bus.

It then waits for the device to initiate the Connect sequence. In device mode once this bit is set, the device waits for the HSIC Idle line state on the bus. Upon receving the Idle line state, it initiates the HSIC Connect sequence.

Definition at line 375 of file dwc_otg_regs.h.


The documentation for this union was generated from the following file:
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  doxygen 1.4.7