#include <dwc_otg_regs.h>
Data Fields | |
uint32_t | d32 |
raw register data | |
struct { | |
unsigned mps:11 | |
Maximum packet size in bytes. | |
unsigned epnum:4 | |
Endpoint number. | |
unsigned epdir:1 | |
0: OUT, 1: IN | |
unsigned reserved:1 | |
unsigned lspddev:1 | |
0: Full/high speed device, 1: Low speed device | |
unsigned eptype:2 | |
0: Control, 1: Isoc, 2: Bulk, 3: Intr | |
unsigned multicnt:2 | |
Packets per frame for periodic transfers. | |
unsigned devaddr:7 | |
Device address. | |
unsigned oddfrm:1 | |
Frame to transmit periodic transaction. | |
unsigned chdis:1 | |
Channel disable. | |
unsigned chen:1 | |
Channel enable. | |
} | b |
register bits |
Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hcchar register.
Definition at line 1863 of file dwc_otg_regs.h.
unsigned hcchar_data::multicnt |
Packets per frame for periodic transfers.
0 is reserved.
Definition at line 1887 of file dwc_otg_regs.h.
unsigned hcchar_data::oddfrm |
Frame to transmit periodic transaction.
0: even, 1: odd
Definition at line 1896 of file dwc_otg_regs.h.