#include <dwc_otg_regs.h>
Data Fields | |
uint32_t | d32 |
raw register data | |
struct { | |
unsigned xfercomp:1 | |
Transfer Complete. | |
unsigned chhltd:1 | |
Channel Halted. | |
unsigned ahberr:1 | |
AHB Error. | |
unsigned stall:1 | |
STALL Response Received. | |
unsigned nak:1 | |
NAK Response Received. | |
unsigned ack:1 | |
ACK Response Received. | |
unsigned nyet:1 | |
NYET Response Received. | |
unsigned xacterr:1 | |
Transaction Err. | |
unsigned bblerr:1 | |
Babble Error. | |
unsigned frmovrun:1 | |
Frame Overrun. | |
unsigned datatglerr:1 | |
Data Toggle Error. | |
unsigned bna: 1 | |
Buffer Not Available (only for DDMA mode). | |
unsigned xcs_xact: 1 | |
Exessive transaction error (only for DDMA mode). | |
unsigned frm_list_roll: 1 | |
Frame List Rollover interrupt. | |
unsigned reserved14_31: 18 | |
Reserved. | |
} | b |
register bits |
Definition at line 1940 of file dwc_otg_regs.h.