dwc_otg_host_global_regs Struct Reference

The Host Global Registers structure defines the size and relative field offsets for the Host Mode Global Registers. More...

#include <dwc_otg_regs.h>


Data Fields

volatile uint32_t hcfg
 Host Configuration Register.
volatile uint32_t hfir
 Host Frame Interval Register.
volatile uint32_t hfnum
 Host Frame Number / Frame Remaining Register.
uint32_t reserved40C
 Reserved.
volatile uint32_t hptxsts
 Host Periodic Transmit FIFO/ Queue Status Register.
volatile uint32_t haint
 Host All Channels Interrupt Register.
volatile uint32_t haintmsk
 Host All Channels Interrupt Mask Register.
volatile uint32_t hflbaddr
 Host Frame List Base Address Register .


Detailed Description

The Host Global Registers structure defines the size and relative field offsets for the Host Mode Global Registers.

Host Global Registers offsets 400h-7FFh.

Definition at line 1627 of file dwc_otg_regs.h.


Field Documentation

volatile uint32_t dwc_otg_host_global_regs::hcfg

Host Configuration Register.

Offset: 400h

Definition at line 1629 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_host_global_regs::hfir

Host Frame Interval Register.

Offset: 404h

Definition at line 1631 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_host_global_regs::hfnum

Host Frame Number / Frame Remaining Register.

Offset: 408h

Definition at line 1633 of file dwc_otg_regs.h.

uint32_t dwc_otg_host_global_regs::reserved40C

Reserved.

Offset: 40Ch

Definition at line 1635 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_host_global_regs::hptxsts

Host Periodic Transmit FIFO/ Queue Status Register.

Offset: 410h

Definition at line 1637 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_host_global_regs::haint

Host All Channels Interrupt Register.

Offset: 414h

Definition at line 1639 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_host_global_regs::haintmsk

Host All Channels Interrupt Mask Register.

Offset: 418h

Definition at line 1641 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_host_global_regs::hflbaddr

Host Frame List Base Address Register .

Offset: 41Ch

Definition at line 1643 of file dwc_otg_regs.h.


The documentation for this struct was generated from the following file:
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  doxygen 1.4.7