#include <dwc_otg_regs.h>
Data Fields | |
uint32_t | d32 |
raw register data | |
struct { | |
unsigned fslspclksel:2 | |
FS/LS Phy Clock Select. | |
unsigned fslssupp:1 | |
FS/LS Only Support. | |
unsigned reserved3_22: 20 | |
unsigned descdma: 1 | |
Enable Scatter/gather DMA in Host mode. | |
unsigned frlisten: 2 | |
Frame List Entries. | |
unsigned perschedena: 1 | |
Enable Periodic Scheduling. | |
unsigned perschedstat: 1 | |
Periodic Scheduling Enabled Status. | |
} | b |
register bits |
Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hcfg register.
Definition at line 1652 of file dwc_otg_regs.h.