#include <dwc_otg_regs.h>
Data Fields | |
volatile uint32_t | doepctl |
Device OUT Endpoint Control Register. | |
volatile uint32_t | doepfn |
Device OUT Endpoint Frame number Register. | |
volatile uint32_t | doepint |
Device OUT Endpoint Interrupt Register. | |
uint32_t | reserved0C |
Reserved. | |
volatile uint32_t | doeptsiz |
Device OUT Endpoint Transfer Size Register. | |
volatile uint32_t | doepdma |
Device OUT Endpoint DMA Address Register. | |
uint32_t | unused |
Reserved. | |
uint32_t | doepdmab |
Device OUT Endpoint DMA Buffer Register. |
Offsets: B00h-CFCh
There will be one set of endpoint registers per logical endpoint implemented.
These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown.
Definition at line 1274 of file dwc_otg_regs.h.
volatile uint32_t dwc_otg_dev_out_ep_regs::doepctl |
Device OUT Endpoint Control Register.
Offset:B00h + (ep_num * 20h) + 00h
Definition at line 1277 of file dwc_otg_regs.h.
volatile uint32_t dwc_otg_dev_out_ep_regs::doepfn |
Device OUT Endpoint Frame number Register.
Offset: B00h + (ep_num * 20h) + 04h
Definition at line 1280 of file dwc_otg_regs.h.
volatile uint32_t dwc_otg_dev_out_ep_regs::doepint |
Device OUT Endpoint Interrupt Register.
Offset:B00h + (ep_num * 20h) + 08h
Definition at line 1283 of file dwc_otg_regs.h.
uint32_t dwc_otg_dev_out_ep_regs::reserved0C |
volatile uint32_t dwc_otg_dev_out_ep_regs::doeptsiz |
Device OUT Endpoint Transfer Size Register.
Offset: B00h + (ep_num * 20h) + 10h
Definition at line 1288 of file dwc_otg_regs.h.
volatile uint32_t dwc_otg_dev_out_ep_regs::doepdma |
Device OUT Endpoint DMA Address Register.
Offset:B00h + (ep_num * 20h) + 14h
Definition at line 1291 of file dwc_otg_regs.h.
uint32_t dwc_otg_dev_out_ep_regs::unused |
uint32_t dwc_otg_dev_out_ep_regs::doepdmab |
Device OUT Endpoint DMA Buffer Register.
Offset:B00h + (ep_num * 20h) + 1Ch
Definition at line 1296 of file dwc_otg_regs.h.