#include <dwc_otg_regs.h>
Data Fields | |
| dwc_otg_device_global_regs_t * | dev_global_regs |
| Pointer to device Global registers. | |
| dwc_otg_dev_in_ep_regs_t * | in_ep_regs [MAX_EPS_CHANNELS] |
| Device Logical IN Endpoint-Specific Registers 900h-AFCh. | |
| dwc_otg_dev_out_ep_regs_t * | out_ep_regs [MAX_EPS_CHANNELS] |
| Device Logical OUT Endpoint-Specific Registers B00h-CFCh. | |
| uint8_t | speed |
| Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS. | |
| uint8_t | num_in_eps |
| Number # of Tx EP range: 0-15 exept ep0. | |
| uint8_t | num_out_eps |
| Number # of Rx EP range: 0-15 exept ep 0. | |
| uint16_t | perio_tx_fifo_size [MAX_PERIO_FIFOS] |
| Size of periodic FIFOs (Bytes). | |
| uint16_t | tx_fifo_size [MAX_TX_FIFOS] |
| Size of Tx FIFOs (Bytes). | |
| uint16_t | rx_thr_en |
| Thresholding enable flags and length varaiables. | |
| uint16_t | iso_tx_thr_en |
| uint16_t | non_iso_tx_thr_en |
| uint16_t | rx_thr_length |
| uint16_t | tx_thr_length |
| dwc_dma_t | dma_setup_desc_addr [2] |
| 2 descriptors for SETUP packets | |
| dwc_otg_dev_dma_desc_t * | setup_desc_addr [2] |
| dwc_otg_dev_dma_desc_t * | psetup |
| Pointer to Descriptor with latest SETUP packet. | |
| uint32_t | setup_desc_index |
| Index of current SETUP handler descriptor. | |
| dwc_dma_t | dma_in_desc_addr |
| Descriptor for Data In or Status In phases. | |
| dwc_otg_dev_dma_desc_t * | in_desc_addr |
| dwc_dma_t | dma_out_desc_addr |
| Descriptor for Data Out or Status Out phases. | |
| dwc_otg_dev_dma_desc_t * | out_desc_addr |
| uint32_t | spd |
| Setup Packet Detected - if set clear NAK when queueing. | |
It represents the programming view of the device-specific aspects of the controller.
Definition at line 1554 of file dwc_otg_regs.h.
Pointer to device Global registers.
Device Global Registers starting at offset 800h
Definition at line 1558 of file dwc_otg_regs.h.
1.4.7