#include <dwc_otg_regs.h>
Data Fields | |
volatile uint32_t | diepctl |
Device IN Endpoint Control Register. | |
uint32_t | reserved04 |
Reserved. | |
volatile uint32_t | diepint |
Device IN Endpoint Interrupt Register. | |
uint32_t | reserved0C |
Reserved. | |
volatile uint32_t | dieptsiz |
Device IN Endpoint Transfer Size Register. | |
volatile uint32_t | diepdma |
Device IN Endpoint DMA Address Register. | |
volatile uint32_t | dtxfsts |
Device IN Endpoint Transmit FIFO Status Register. | |
volatile uint32_t | diepdmab |
Device IN Endpoint DMA Buffer Register. |
Offsets 900h-AFCh
There will be one set of endpoint registers per logical endpoint implemented.
These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown.
Definition at line 1239 of file dwc_otg_regs.h.
volatile uint32_t dwc_otg_dev_in_ep_regs::diepctl |
Device IN Endpoint Control Register.
Offset:900h + (ep_num * 20h) + 00h
Definition at line 1242 of file dwc_otg_regs.h.
uint32_t dwc_otg_dev_in_ep_regs::reserved04 |
volatile uint32_t dwc_otg_dev_in_ep_regs::diepint |
Device IN Endpoint Interrupt Register.
Offset:900h + (ep_num * 20h) + 08h
Definition at line 1247 of file dwc_otg_regs.h.
uint32_t dwc_otg_dev_in_ep_regs::reserved0C |
volatile uint32_t dwc_otg_dev_in_ep_regs::dieptsiz |
Device IN Endpoint Transfer Size Register.
Offset:900h + (ep_num * 20h) + 10h
Definition at line 1252 of file dwc_otg_regs.h.
volatile uint32_t dwc_otg_dev_in_ep_regs::diepdma |
Device IN Endpoint DMA Address Register.
Offset:900h + (ep_num * 20h) + 14h
Definition at line 1255 of file dwc_otg_regs.h.
volatile uint32_t dwc_otg_dev_in_ep_regs::dtxfsts |
Device IN Endpoint Transmit FIFO Status Register.
Offset:900h + (ep_num * 20h) + 18h
Definition at line 1258 of file dwc_otg_regs.h.
volatile uint32_t dwc_otg_dev_in_ep_regs::diepdmab |
Device IN Endpoint DMA Buffer Register.
Offset:900h + (ep_num * 20h) + 1Ch
Definition at line 1261 of file dwc_otg_regs.h.