dwc_otg_dev_global_regs Struct Reference

Device Global Registers. More...

#include <dwc_otg_regs.h>

Data Fields
volatile uint32_t	dcfg
	Device Configuration Register.
volatile uint32_t	dctl
	Device Control Register.
volatile uint32_t	dsts
	Device Status Register (Read Only).
uint32_t	unused
	Reserved.
volatile uint32_t	diepmsk
	Device IN Endpoint Common Interrupt Mask Register.
volatile uint32_t	doepmsk
	Device OUT Endpoint Common Interrupt Mask Register.
volatile uint32_t	daint
	Device All Endpoints Interrupt Register.
volatile uint32_t	daintmsk
	Device All Endpoints Interrupt Mask Register.
volatile uint32_t	dtknqr1
	Device IN Token Queue Read Register-1 (Read Only).
volatile uint32_t	dtknqr2
	Device IN Token Queue Read Register-2 (Read Only).
volatile uint32_t	dvbusdis
	Device VBUS discharge Register.
volatile uint32_t	dvbuspulse
	Device VBUS Pulse Register.
volatile uint32_t	dtknqr3_dthrctl
	Device IN Token Queue Read Register-3 (Read Only).
volatile uint32_t	dtknqr4_fifoemptymsk
	Device IN Token Queue Read Register-4 (Read Only).
volatile uint32_t	deachint
	Device Each Endpoint Interrupt Register (Read Only).
volatile uint32_t	deachintmsk
	Device Each Endpoint Interrupt mask Register (Read/Write).
volatile uint32_t	diepeachintmsk [MAX_EPS_CHANNELS]
	Device Each In Endpoint Interrupt mask Register (Read/Write).
volatile uint32_t	doepeachintmsk [MAX_EPS_CHANNELS]
	Device Each Out Endpoint Interrupt mask Register (Read/Write).

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Detailed Description

Device Global Registers.

Offsets 800h-BFFh

The following structures define the size and relative field offsets for the Device Mode Registers.

These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown.

Definition at line 865 of file dwc_otg_regs.h.

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Field Documentation

volatile uint32_t dwc_otg_dev_global_regs::dcfg

Device Configuration Register.

Offset 800h

Definition at line 867 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_dev_global_regs::dctl

Device Control Register.

Offset: 804h

Definition at line 869 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_dev_global_regs::dsts

Device Status Register (Read Only).

Offset: 808h

Definition at line 871 of file dwc_otg_regs.h.

uint32_t dwc_otg_dev_global_regs::unused

Reserved.

Offset: 80Ch

Definition at line 873 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_dev_global_regs::diepmsk

Device IN Endpoint Common Interrupt Mask Register.

Offset: 810h

Definition at line 876 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_dev_global_regs::doepmsk

Device OUT Endpoint Common Interrupt Mask Register.

Offset: 814h

Definition at line 879 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_dev_global_regs::daint

Device All Endpoints Interrupt Register.

Offset: 818h

Definition at line 881 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_dev_global_regs::daintmsk

Device All Endpoints Interrupt Mask Register.

Offset: 81Ch

Definition at line 884 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_dev_global_regs::dtknqr1

Device IN Token Queue Read Register-1 (Read Only).

Offset: 820h

Definition at line 887 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_dev_global_regs::dtknqr2

Device IN Token Queue Read Register-2 (Read Only).

Offset: 824h

Definition at line 890 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_dev_global_regs::dvbusdis

Device VBUS discharge Register.

Offset: 828h

Definition at line 892 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_dev_global_regs::dvbuspulse

Device VBUS Pulse Register.

Offset: 82Ch

Definition at line 894 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_dev_global_regs::dtknqr3_dthrctl

Device IN Token Queue Read Register-3 (Read Only).

/ Device Thresholding control register (Read/Write) Offset: 830h

Definition at line 898 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_dev_global_regs::dtknqr4_fifoemptymsk

Device IN Token Queue Read Register-4 (Read Only).

/ Device IN EPs empty Inr. Mask Register (Read/Write) Offset: 834h

Definition at line 902 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_dev_global_regs::deachint

Device Each Endpoint Interrupt Register (Read Only).

/ Offset: 838h

Definition at line 905 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_dev_global_regs::deachintmsk

Device Each Endpoint Interrupt mask Register (Read/Write).

/ Offset: 83Ch

Definition at line 908 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_dev_global_regs::diepeachintmsk[MAX_EPS_CHANNELS]

Device Each In Endpoint Interrupt mask Register (Read/Write).

/ Offset: 840h

Definition at line 911 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_dev_global_regs::doepeachintmsk[MAX_EPS_CHANNELS]

Device Each Out Endpoint Interrupt mask Register (Read/Write).

/ Offset: 880h

Definition at line 914 of file dwc_otg_regs.h.

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The documentation for this struct was generated from the following file:

• dwc_otg_regs.h

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