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Tests and Test Results

Tests cited by name in the paper

  ModelCortexA9Tegra2
2+2WAllow=Ok, 7.4M/3.0G
2+2W+dmbsForbid=Ok, 0/3.0G
2+2W+readsAllow
2+2W+dmbs+readsForbid
CoRR1Forbid=
CoRR2Forbid=
CoRWForbid=Ok, 0/3.0G
CoWRForbid=Ok, 0/3.0G
CoWWForbid=Ok, 0/6.0G
LB+rsAllow=Ok, 43k/402MOk, 99k/3.0G
MP+dmb+rsAllow=Ok, 243k/402MOk, 9.0M/3.0G
MP+nondep+dmbAllow=Ok, 7.2k/402MOk, 2.2M/3.0G
PPOAAForbid=Ok, 0/402MOk, 0/3.0G
PPOCAAllow=No, 0/402MNo, 0/3.0G
   Allow unseenAllow unseen
RDWForbid=
RDWIAllow=No, 0/402MNo, 0/3.0G
   Allow unseenAllow unseen
RSWAllow=No, 0/402MNo, 0/3.0G
   Allow unseenAllow unseen
IRIWAllow=
IRIW+addrsAllow=
IRIW+dmbsForbid
IRIW+dsbsForbid
ISA2+dmb+data+addrForbid=
LBAllow=Ok, 239k/402MOk, 1.4M/3.0G
LB+addrsForbid=Ok, 0/402MOk, 0/3.0G
LB+datasForbid=Ok, 0/402MOk, 0/3.0G
LB+dmbsForbid=Ok, 0/402MOk, 0/3.0G
LB+dsbsForbid=Ok, 0/402MOk, 0/3.0G
MPAllow=Ok, 824k/402MOk, 2.1M/3.0G
MP+po+addrAllow=Ok, 285k/402MOk, 624k/3.0G
MP+dmb+addrForbid=Ok, 0/402MOk, 0/3.0G
MP+dsb+addrForbid=Ok, 0/402MOk, 0/3.0G
MP+dmb+ctrlAllow=Ok, 218k/402MOk, 5.7M/3.0G
MP+dsb+ctrlAllow=Ok, 233k/402MOk, 5.4M/3.0G
MP+dmb+ctrlisbForbid=Ok, 0/402MOk, 0/3.0G
MP+dsb+ctrlisbForbid=Ok, 0/402MOk, 0/3.0G
MP+dmbsForbid=Ok, 0/402MOk, 0/3.0G
MP+dsbsForbid=Ok, 0/402MOk, 0/3.0G
SBAllow=Ok, 3.6M/402MOk, 72M/3.0G
SB+dmbsForbid=Ok, 0/402MOk, 0/3.0G
SB+dsbsForbid=Ok, 0/402MOk, 0/3.0G
WRCAllow=
WRC+data+addrAllow=
WRC+dmb+addrForbid=
WRC+dsb+addrForbid=
WRC+data+dmbAllow=
WRC+dmbsForbid=
WRC+data+dsbAllow=
WRC+dsbsForbid=

Systematic tests

These tests are generated using the diycross tool, a variant of diy. They are systematic variations of a number of families, inserting different choices of barriers or dependencies. The families themselves are also systematic, as follows.

Consider tests built from a cycle of edges of the following four kinds: program order (po) (perhaps with barriers or dependencies); reads-from (rf) edges, from a write to a read that reads from it; from-reads (fr) edges, from a read to coherence-successors of the write it reads from; and coherence (co) edges, from a write to a coherence-later write to the same address. In the diagrams below reads from the initial state are shown as rf edges from a red dot; the fr edges are not shown explicitly but go from such reads to the write that is to the same address.

There are six two-thread cycles with four edges, as in the left-hand column of the table below: test families MP, SB, LB, R, S, and 2+2W. MP and SB are the classic ‘message-passing’ and ‘store-buffering’ tests.

For all those test families except LB and R, there is an obvious three-thread analogue in which the initial write is replaced by a read from a write pulled out to another thread, as in the middle column below. The analogues of MP and SB are the classic WRC and RWC tests (as in Boehm and Adve, PLDI 2008). For R there are two three-thread analogues, pulling back the writes of the two threads: WRW+WR and WRR+2W.

MP: rf,fr
WRC: rf,rf,fr
 
SB: fr,fr
RWC: rf,fr,fr
 
LB: rf,rf
  
R: co,fr
WRW+WR: rf,co,fr
WRR+2W: rf,fr,co
S: rf,co
WWC: rf,rf,co
 
2+2W: co,co
WRW+2W: rf,co,co
 

The ISA2 family (based on the second example in the Power 2.06 ISA, illustrating B-cumulativity) is a three-thread six-edge test, which one could think of as MP with the first write pulled back along a barrier;rf path, or as WRC with the first write pulled back along a barrier edge:

 
ISA2: rf,rf,fr

There are many other three-thread six-edge tests, some of which we have explored but do not give here.

The IRIW family is a four-thread six-edge test:

 
IRIW: rf,fr,rf,fr

All the tests above have at most one edge on each thread. The PPO family (tests of preserved program order) are variations of MP with a barrier on the writing thread and various combinations of edges on the reading thread.

MP: Message Passing

  ModelCortexA9Tegra2
MPAllow=Ok, 824k/402MOk, 2.1M/3.0G
MP+isb+poAllow=Ok, 541k/402MOk, 34M/3.0G
MP+dmb+poAllow=Ok, 168k/402MOk, 3.1M/3.0G
MP+dsb+poAllow=Ok, 171k/402MOk, 3.0M/3.0G
MP+po+addrAllow=Ok, 285k/402MOk, 624k/3.0G
MP+isb+addrAllow=Ok, 392k/402MOk, 22M/3.0G
MP+dmb+addrForbid=Ok, 0/402MOk, 0/3.0G
MP+dsb+addrForbid=Ok, 0/402MOk, 0/3.0G
MP+po+ctrlAllow=Ok, 600k/402MOk, 4.3M/3.0G
MP+isb+ctrlAllow=Ok, 579k/402MOk, 25M/3.0G
MP+dmb+ctrlAllow=Ok, 218k/402MOk, 5.7M/3.0G
MP+dsb+ctrlAllow=Ok, 233k/402MOk, 5.4M/3.0G
MP+po+ctrlisbAllow=Ok, 388k/402MOk, 1.0M/3.0G
MP+isb+ctrlisbAllow=Ok, 420k/402MOk, 21M/3.0G
MP+dmb+ctrlisbForbid=Ok, 0/402MOk, 0/3.0G
MP+dsb+ctrlisbForbid=Ok, 0/402MOk, 0/3.0G
MP+po+isbAllow=Ok, 622k/402MOk, 2.8M/3.0G
MP+isbsAllow=Ok, 653k/402MOk, 33M/3.0G
MP+dmb+isbAllow=Ok, 254k/402MOk, 1.0M/3.0G
MP+dsb+isbAllow=Ok, 273k/402MOk, 971k/3.0G
MP+po+dmbAllow=Ok, 317k/402MOk, 606k/3.0G
MP+isb+dmbAllow=Ok, 450k/402MOk, 16M/3.0G
MP+dmbsForbid=Ok, 0/402MOk, 0/3.0G
MP+dsb+dmbForbid=Ok, 0/402MOk, 0/3.0G
MP+po+dsbAllow=Ok, 304k/402MOk, 682k/3.0G
MP+isb+dsbAllow=Ok, 394k/402MOk, 13M/3.0G
MP+dmb+dsbForbid=Ok, 0/402MOk, 0/3.0G
MP+dsbsForbid=Ok, 0/402MOk, 0/3.0G

SB: Store Buffer forwarding (sometimes called Dekker’s example)

  ModelCortexA9Tegra2
SBAllow=Ok, 3.6M/402MOk, 72M/3.0G
SB+isb+poAllow=Ok, 3.9M/402MOk, 141M/3.0G
SB+dmb+poAllow=Ok, 1.6M/402MOk, 11M/3.0G
SB+dsb+poAllow=Ok, 1.4M/402MOk, 11M/3.0G
SB+isbsAllow=Ok, 2.1M/402MOk, 199M/3.0G
SB+dmb+isbAllow=Ok, 658k/402MOk, 28M/3.0G
SB+dsb+isbAllow=Ok, 638k/402MOk, 28M/3.0G
SB+dmbsForbid=Ok, 0/402MOk, 0/3.0G
SB+dsb+dmbForbid=Ok, 0/402MOk, 0/3.0G
SB+dsbsForbid=Ok, 0/402MOk, 0/3.0G

LB: Load Buffering

  ModelCortexA9Tegra2
LBAllow=Ok, 239k/402MOk, 1.4M/3.0G
LB+addr+poAllow=Ok, 80k/402MOk, 555k/3.0G
LB+data+poAllow=Ok, 72k/402MOk, 522k/3.0G
LB+ctrl+poAllow=Ok, 77k/402MOk, 559k/3.0G
LB+ctrlisb+poAllow=Ok, 46k/402MOk, 267k/3.0G
LB+isb+poAllow=Ok, 135k/402MOk, 1.1M/3.0G
LB+dmb+poAllow=Ok, 5.4k/402MOk, 14k/3.0G
LB+dsb+poAllow=Ok, 7.3k/402MOk, 15k/3.0G
LB+addrsForbid=Ok, 0/402MOk, 0/3.0G
LB+data+addrForbid=Ok, 0/402MOk, 0/3.0G
LB+ctrl+addrForbid=Ok, 0/402MOk, 0/3.0G
LB+ctrlisb+addrForbid=Ok, 0/402MOk, 0/3.0G
LB+isb+addrAllow=Ok, 15k/402MOk, 82k/3.0G
LB+dmb+addrForbid=Ok, 0/402MOk, 0/3.0G
LB+dsb+addrForbid=Ok, 0/402MOk, 0/3.0G
LB+datasForbid=Ok, 0/402MOk, 0/3.0G
LB+ctrl+dataForbid=Ok, 0/402MOk, 0/3.0G
LB+ctrlisb+dataForbid=Ok, 0/402MOk, 0/3.0G
LB+isb+dataAllow=Ok, 17k/402MOk, 163k/3.0G
LB+dmb+dataForbid=Ok, 0/402MOk, 0/3.0G
LB+dsb+dataForbid=Ok, 0/402MOk, 0/3.0G
LB+ctrlsForbid=Ok, 0/402MOk, 0/3.0G
LB+ctrlisb+ctrlForbid=Ok, 0/402MOk, 0/3.0G
LB+isb+ctrlAllow=Ok, 18k/402MOk, 129k/3.0G
LB+dmb+ctrlForbid=Ok, 0/402MOk, 0/3.0G
LB+dsb+ctrlForbid=Ok, 0/402MOk, 0/3.0G
LB+ctrlisbsForbid=Ok, 0/402MOk, 0/3.0G
LB+isb+ctrlisbAllow=Ok, 8.7k/402MOk, 51k/3.0G
LB+dmb+ctrlisbForbid=Ok, 0/402MOk, 0/3.0G
LB+dsb+ctrlisbForbid=Ok, 0/402MOk, 0/3.0G
LB+isbsAllow=Ok, 38k/402MOk, 494k/3.0G
LB+dmb+isbAllow=Ok, 2.2k/402MOk, 9.4k/3.0G
LB+dsb+isbAllow=Ok, 1.9k/402MOk, 8.7k/3.0G
LB+dmbsForbid=Ok, 0/402MOk, 0/3.0G
LB+dsb+dmbForbid=Ok, 0/402MOk, 0/3.0G
LB+dsbsForbid=Ok, 0/402MOk, 0/3.0G

IRIW: Independent Reads of Independent Writes

  ModelCortexA9Tegra2
IRIWAllow=
IRIW+addr+poAllow=
IRIW+ctrl+poAllow=
IRIW+ctrlisb+poAllow=
IRIW+isb+poAllow=
IRIW+dmb+poAllow=
IRIW+dsb+poAllow=
IRIW+addrsAllow=
IRIW+ctrl+addrAllow=
IRIW+ctrlisb+addrAllow=
IRIW+isb+addrAllow=
IRIW+dmb+addrAllow=
IRIW+dsb+addrAllow=
IRIW+ctrlsAllow=
IRIW+ctrlisb+ctrlAllow=
IRIW+isb+ctrlAllow=
IRIW+dmb+ctrlAllow=
IRIW+dsb+ctrlAllow=
IRIW+ctrlisbsAllow=
IRIW+isb+ctrlisbAllow=
IRIW+dmb+ctrlisbAllow=
IRIW+dsb+ctrlisbAllow=
IRIW+isbsAllow=
IRIW+dmb+isbAllow=
IRIW+dsb+isbAllow=
IRIW+dmbsForbid
IRIW+dsb+dmbForbid
IRIW+dsbsForbid

WRC: Write to Read Causality

  ModelCortexA9Tegra2
WRCAllow=
WRC+addr+poAllow=
WRC+data+poAllow=
WRC+ctrl+poAllow=
WRC+ctrlisb+poAllow=
WRC+isb+poAllow=
WRC+dmb+poAllow=
WRC+dsb+poAllow=
WRC+po+addrAllow=
WRC+addrsAllow=
WRC+data+addrAllow=
WRC+ctrl+addrAllow=
WRC+ctrlisb+addrAllow=
WRC+isb+addrAllow=
WRC+dmb+addrForbid=
WRC+dsb+addrForbid=
WRC+po+ctrlAllow=
WRC+addr+ctrlAllow=
WRC+data+ctrlAllow=
WRC+ctrlsAllow=
WRC+ctrlisb+ctrlAllow=
WRC+isb+ctrlAllow=
WRC+dmb+ctrlAllow=
WRC+dsb+ctrlAllow=
WRC+po+ctrlisbAllow=
WRC+addr+ctrlisbAllow=
WRC+data+ctrlisbAllow=
WRC+ctrl+ctrlisbAllow=
WRC+ctrlisbsAllow=
WRC+isb+ctrlisbAllow=
WRC+dmb+ctrlisbForbid=
WRC+dsb+ctrlisbForbid=
WRC+po+isbAllow=
WRC+addr+isbAllow=
WRC+data+isbAllow=
WRC+ctrl+isbAllow=
WRC+ctrlisb+isbAllow=
WRC+isbsAllow=
WRC+dmb+isbAllow=
WRC+dsb+isbAllow=
WRC+po+dmbAllow=
WRC+addr+dmbAllow=
WRC+data+dmbAllow=
WRC+ctrl+dmbAllow=
WRC+ctrlisb+dmbAllow=
WRC+isb+dmbAllow=
WRC+dmbsForbid=
WRC+dsb+dmbForbid=
WRC+po+dsbAllow=
WRC+addr+dsbAllow=
WRC+data+dsbAllow=
WRC+ctrl+dsbAllow=
WRC+ctrlisb+dsbAllow=
WRC+isb+dsbAllow=
WRC+dmb+dsbForbid=
WRC+dsbsForbid=

RWC: Read to Write Causality

  ModelCortexA9Tegra2
RWCAllow=
RWC+addr+poAllow=
RWC+ctrl+poAllow=
RWC+ctrlisb+poAllow=
RWC+isb+poAllow=
RWC+dmb+poAllow=
RWC+dsb+poAllow=
RWC+po+isbAllow=
RWC+addr+isbAllow=
RWC+ctrl+isbAllow=
RWC+ctrlisb+isbAllow=
RWC+isbsAllow=
RWC+dmb+isbAllow=
RWC+dsb+isbAllow=
RWC+po+dmbAllow=
RWC+addr+dmbAllow=
RWC+ctrl+dmbAllow=
RWC+ctrlisb+dmbAllow=
RWC+isb+dmbAllow=
RWC+dmbsForbid=
RWC+dsb+dmbForbid=
RWC+po+dsbAllow=
RWC+addr+dsbAllow=
RWC+ctrl+dsbAllow=
RWC+ctrlisb+dsbAllow=
RWC+isb+dsbAllow=
RWC+dmb+dsbForbid=
RWC+dsbsForbid=

ISA2: Second example from POWER documentation

  ModelCortexA9Tegra2
ISA2+dmb+po+poAllow=
ISA2+dmb+addr+poAllow=
ISA2+dmb+data+poAllow=
ISA2+dmb+ctrl+poAllow=
ISA2+dmb+ctrlisb+poAllow=
ISA2+dmb+isb+poAllow=
ISA2+dmb+dmb+poAllow=
ISA2+dmb+dsb+poAllow=
ISA2+dmb+po+addrAllow=
ISA2+dmb+addr+addrForbid=
ISA2+dmb+data+addrForbid=
ISA2+dmb+ctrl+addrForbid=
ISA2+dmb+ctrlisb+addrForbid=
ISA2+dmb+isb+addrAllow=
ISA2+dmb+dmb+addrForbid=
ISA2+dmb+dsb+addrForbid=
ISA2+dmb+po+ctrlAllow=
ISA2+dmb+addr+ctrlAllow=
ISA2+dmb+data+ctrlAllow=
ISA2+dmb+ctrl+ctrlAllow=
ISA2+dmb+ctrlisb+ctrlAllow=
ISA2+dmb+isb+ctrlAllow=
ISA2+dmb+dmb+ctrlAllow=
ISA2+dmb+dsb+ctrlAllow=
ISA2+dmb+po+ctrlisbAllow=
ISA2+dmb+addr+ctrlisbForbid=
ISA2+dmb+data+ctrlisbForbid=
ISA2+dmb+ctrl+ctrlisbForbid=
ISA2+dmb+ctrlisb+ctrlisbForbid=
ISA2+dmb+isb+ctrlisbAllow=
ISA2+dmb+dmb+ctrlisbForbid=
ISA2+dmb+dsb+ctrlisbForbid=
ISA2+dmb+po+isbAllow=
ISA2+dmb+addr+isbAllow=
ISA2+dmb+data+isbAllow=
ISA2+dmb+ctrl+isbAllow=
ISA2+dmb+ctrlisb+isbAllow=
ISA2+dmb+isb+isbAllow=
ISA2+dmb+dmb+isbAllow=
ISA2+dmb+dsb+isbAllow=
ISA2+dmb+po+dmbAllow=
ISA2+dmb+addr+dmbForbid=
ISA2+dmb+data+dmbForbid=
ISA2+dmb+ctrl+dmbForbid=
ISA2+dmb+ctrlisb+dmbForbid=
ISA2+dmb+isb+dmbAllow=
ISA2+dmbsForbid=
ISA2+dmb+dsb+dmbForbid=
ISA2+dmb+po+dsbAllow=
ISA2+dmb+addr+dsbForbid=
ISA2+dmb+data+dsbForbid=
ISA2+dmb+ctrl+dsbForbid=
ISA2+dmb+ctrlisb+dsbForbid=
ISA2+dmb+isb+dsbAllow=
ISA2+dmb+dmb+dsbForbid=
ISA2+dmb+dsb+dsbForbid=

2+2W:

  ModelCortexA9Tegra2
2+2WAllow=Ok, 7.4M/3.0G
2+2W+dmbsForbid=Ok, 0/3.0G
2+2W+isb+poAllow=Ok, 19M/3.0G
2+2W+isbsAllow=Ok, 38M/3.0G
2+2W+dmb+poAllow=Ok, 1.4M/3.0G
2+2W+dmb+isbAllow=Ok, 4.9M/3.0G
2+2W+dsb+poAllow=Ok, 1.7M/3.0G
2+2W+dsb+isbAllow=Ok, 5.4M/3.0G
2+2W+dsb+dmbForbid=Ok, 0/3.0G
2+2W+dsbsForbid=Ok, 0/3.0G

R:

  ModelCortexA9Tegra2
RAllow=Ok, 1.9M/170MOk, 32M/3.0G
R+isb+poAllow=Ok, 2.3M/170MOk, 102M/3.0G
R+dmb+poAllow=Ok, 147k/170MOk, 18M/3.0G
R+dsb+poAllow=Ok, 137k/170MOk, 18M/3.0G
R+po+isbAllow=Ok, 2.6M/170MOk, 100M/3.0G
R+isbsAllow=Ok, 1.8M/170MOk, 148M/3.0G
R+dmb+isbAllow=Ok, 81k/170MOk, 46M/3.0G
R+dsb+isbAllow=Ok, 75k/170MOk, 46M/3.0G
R+po+dmbAllow=Ok, 467k/170MOk, 741k/3.0G
R+isb+dmbAllow=Ok, 667k/170MOk, 45M/3.0G
R+dmbsForbid=Ok, 0/170MOk, 0/3.0G
R+dsb+dmbForbid=Ok, 0/170MOk, 0/3.0G
R+po+dsbAllow=Ok, 579k/170MOk, 712k/3.0G
R+isb+dsbAllow=Ok, 661k/170MOk, 42M/3.0G
R+dmb+dsbForbid=Ok, 0/170MOk, 0/3.0G
R+dsbsForbid=Ok, 0/170MOk, 0/3.0G

S:

  ModelCortexA9Tegra2
SAllow=Ok, 711k/170MOk, 4.6M/3.0G
S+isb+poAllow=Ok, 573k/170MOk, 58M/3.0G
S+dmb+poAllow=Ok, 81k/170MOk, 270k/3.0G
S+dsb+poAllow=Ok, 73k/170MOk, 239k/3.0G
S+po+addrAllow=Ok, 919k/170MOk, 1.7M/3.0G
S+isb+addrAllow=Ok, 349k/170MOk, 50M/3.0G
S+dmb+addrForbid=Ok, 0/170MOk, 0/3.0G
S+dsb+addrForbid=Ok, 0/170MOk, 0/3.0G
S+po+dataAllow=Ok, 541k/170MOk, 1.8M/3.0G
S+isb+dataAllow=Ok, 457k/170MOk, 36M/3.0G
S+dmb+dataForbid=Ok, 0/170MOk, 0/3.0G
S+dsb+dataForbid=Ok, 0/170MOk, 0/3.0G
S+po+ctrlAllow=Ok, 523k/170MOk, 1.9M/3.0G
S+isb+ctrlAllow=Ok, 474k/170MOk, 47M/3.0G
S+dmb+ctrlForbid=Ok, 0/170MOk, 0/3.0G
S+dsb+ctrlForbid=Ok, 0/170MOk, 0/3.0G
S+po+ctrlisbAllow=Ok, 148k/170MOk, 1.3M/3.0G
S+isb+ctrlisbAllow=Ok, 236k/170MOk, 29M/3.0G
S+dmb+ctrlisbForbid=Ok, 0/170MOk, 0/3.0G
S+dsb+ctrlisbForbid=Ok, 0/170MOk, 0/3.0G
S+po+isbAllow=Ok, 684k/170MOk, 2.7M/3.0G
S+isbsAllow=Ok, 555k/170MOk, 60M/3.0G
S+dmb+isbAllow=Ok, 13k/170MOk, 253k/3.0G
S+dsb+isbAllow=Ok, 11k/170MOk, 227k/3.0G
S+po+dmbAllow=Ok, 70k/170MOk, 316k/3.0G
S+isb+dmbAllow=Ok, 133k/170MOk, 12M/3.0G
S+dmbsForbid=Ok, 0/170MOk, 0/3.0G
S+dsb+dmbForbid=Ok, 0/170MOk, 0/3.0G
S+po+dsbAllow=Ok, 66k/170MOk, 480k/3.0G
S+isb+dsbAllow=Ok, 132k/170MOk, 11M/3.0G
S+dmb+dsbForbid=Ok, 0/170MOk, 0/3.0G
S+dsbsForbid=Ok, 0/170MOk, 0/3.0G

WWC:

  ModelCortexA9Tegra2
WWCAllow=
WWC+addr+dmbAllow=
WWC+addr+poAllow=
WWC+addrsAllow=
WWC+dmb+addrForbid=
WWC+dmb+poAllow=
WWC+dmbsForbid=
WWC+po+addrAllow=
WWC+po+dmbAllow=

WRW+2W:

  ModelCortexA9Tegra2
WRW+2WAllow=
WRW+2W+addr+poAllow=
WRW+2W+dmb+poAllow=
WRW+2W+po+isbAllow=
WRW+2W+addr+isbAllow=
WRW+2W+dmb+isbAllow=
WRW+2W+po+dmbAllow=
WRW+2W+addr+dmbAllow=
WRW+2W+dmbsForbid=
WRW+2W+po+dsbAllow=
WRW+2W+addr+dsbAllow=
WRW+2W+dmb+dsbForbid=

PPO:

  ModelCortexA9Tegra2
PPO000Forbid0/170M0/3.0G
PPO001Allow0/170M0/3.0G
PPO002Allow0/170M0/3.0G
PPO003Allow283k/170M815k/3.0G
PPO004Forbid0/170M0/3.0G
PPO005Allow0/170M0/3.0G
PPO006Allow0/170M0/3.0G
PPO007Allow0/170M0/3.0G
PPO008Allow0/170M0/3.0G
PPO009Forbid0/170M0/3.0G
PPO010Forbid0/170M0/3.0G
PPO011Forbid0/170M0/3.0G
PPO012Forbid0/170M0/3.0G
PPO013Forbid0/170M0/3.0G
PPO014Forbid0/170M0/3.0G
PPO015Forbid0/170M0/3.0G
PPO016Forbid0/170M0/3.0G
PPO017Forbid0/170M0/3.0G
PPO018Forbid0/170M0/3.0G
PPO019Forbid0/170M0/3.0G

Extra tests

  ModelCortexA9Tegra2
DataRWAllow=Ok, 5.6k/2.6G
AddrRWForbid=Ok, 0/14G
DataWWAllow=Ok, 6.1k/2.4G
AddrWWForbid=Ok, 0/2.4G
LB+datas+WWAllow=Ok, 14k/2.4G
LB+addrs+WWForbid=Ok, 0/2.4G

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