Test WRC+addr+ctrl

Run WRC+addr+ctrl in model, using armmem

ARM WRC+addr+ctrl
"Rfe DpAddrdW Rfe DpCtrldR Fre"
Cycle=Rfe DpAddrdW Rfe DpCtrldR Fre
{
%x0=x;
%x1=x; %y1=y;
%y2=y; %x2=x;
}
 P0            | P1               | P2            ;
 MOV R0, #1    | LDR R0, [%x1]    | LDR R0, [%y2] ;
 STR R0, [%x0] | EOR R1,R0,R0     | CMP R0, R0    ;
               | MOV R2, #1       | BNE LC00      ;
               | STR R2, [R1,%y1] | LC00:         ;
               |                  | LDR R1, [%x2] ;
exists
(1:R0=1 /\ 2:R0=1 /\ 2:R1=0)