Test SB+dmb+isb

Run SB+dmb+isb in model, using armmem

ARM SB+dmb+isb
"DMBdWR Fre ISBdWR Fre"
Cycle=Fre DMBdWR Fre ISBdWR
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0            | P1            ;
 MOV R0, #1    | MOV R0, #1    ;
 STR R0, [%x0] | STR R0, [%y1] ;
 DMB           | ISB           ;
 LDR R1, [%y0] | LDR R1, [%x1] ;
exists
(0:R1=0 /\ 1:R1=0)