Test WRC+ctrlisb+isb

Run WRC+ctrlisb+isb in model, using armmem

ARM WRC+ctrlisb+isb
"Rfe DpCtrlIsbdW Rfe ISBdRR Fre"
Cycle=Rfe ISBdRR Fre Rfe DpCtrlIsbdW
{
%x0=x;
%x1=x; %y1=y;
%y2=y; %x2=x;
}
 P0            | P1            | P2            ;
 MOV R0, #1    | LDR R0, [%x1] | LDR R0, [%y2] ;
 STR R0, [%x0] | CMP R0, R0    | ISB           ;
               | BNE LC00      | LDR R1, [%x2] ;
               | LC00:         |               ;
               | ISB           |               ;
               | MOV R1, #1    |               ;
               | STR R1, [%y1] |               ;
exists
(1:R0=1 /\ 2:R0=1 /\ 2:R1=0)