Run RWC+addr+dmb in model, using armmem
ARM RWC+addr+dmb "Rfe DpAddrdR Fre DMBdWR Fre" Cycle=Rfe DpAddrdR Fre DMBdWR Fre { %x0=x; %x1=x; %y1=y; %y2=y; %x2=x; } P0 | P1 | P2 ; MOV R0, #1 | LDR R0, [%x1] | MOV R0, #1 ; STR R0, [%x0] | EOR R1,R0,R0 | STR R0, [%y2] ; | LDR R2, [R1,%y1] | DMB ; | | LDR R1, [%x2] ; exists (1:R0=1 /\ 1:R2=0 /\ 2:R1=0)