Test S+po+ctrlisb

Run S+po+ctrlisb in model, using armmem

ARM S+po+ctrlisb
"PodWW Rfe DpCtrlIsbdW Wse"
Cycle=Rfe DpCtrlIsbdW Wse PodWW
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0            | P1            ;
 MOV R0, #2    | LDR R0, [%y1] ;
 STR R0, [%x0] | CMP R0, R0    ;
 MOV R1, #1    | BNE LC00      ;
 STR R1, [%y0] | LC00:         ;
               | ISB           ;
               | MOV R1, #1    ;
               | STR R1, [%x1] ;
exists
(x=2 /\ 1:R0=1)