Run LB+ctrlisb+addr in model, using armmem
ARM LB+ctrlisb+addr "DpCtrlIsbdW Rfe DpAddrdW Rfe" Cycle=Rfe DpAddrdW Rfe DpCtrlIsbdW { %x0=x; %y0=y; %y1=y; %x1=x; } P0 | P1 ; LDR R0, [%x0] | LDR R0, [%y1] ; CMP R0, R0 | EOR R1,R0,R0 ; BNE LC00 | MOV R2, #1 ; LC00: | STR R2, [R1,%x1] ; ISB | ; MOV R1, #1 | ; STR R1, [%y0] | ; exists (0:R0=1 /\ 1:R0=1)