Test WRC+dsb+ctrl

Run WRC+dsb+ctrl in model, using armmem

ARM WRC+dsb+ctrl
"Rfe DSBdRW Rfe DpCtrldR Fre"
Cycle=Rfe DSBdRW Rfe DpCtrldR Fre
{
%x0=x;
%x1=x; %y1=y;
%y2=y; %x2=x;
}
 P0            | P1            | P2            ;
 MOV R0, #1    | LDR R0, [%x1] | LDR R0, [%y2] ;
 STR R0, [%x0] | DSB           | CMP R0, R0    ;
               | MOV R1, #1    | BNE LC00      ;
               | STR R1, [%y1] | LC00:         ;
               |               | LDR R1, [%x2] ;
exists
(1:R0=1 /\ 2:R0=1 /\ 2:R1=0)