Run WWC+dmb+addr in model, using armmem
ARM WWC+dmb+addr "Rfe DMBdRW Rfe DpAddrdW Wse" Cycle=Rfe DMBdRW Rfe DpAddrdW Wse { %x0=x; %x1=x; %y1=y; %y2=y; %x2=x; } P0 | P1 | P2 ; MOV R0, #2 | LDR R0, [%x1] | LDR R0, [%y2] ; STR R0, [%x0] | DMB | EOR R1,R0,R0 ; | MOV R1, #1 | MOV R2, #1 ; | STR R1, [%y1] | STR R2, [R1,%x2] ; exists (x=2 /\ 1:R0=2 /\ 2:R0=1)