Test WRC+po+dsb

Run WRC+po+dsb in model, using armmem

ARM WRC+po+dsb
"Rfe PodRW Rfe DSBdRR Fre"
Cycle=Rfe PodRW Rfe DSBdRR Fre
{
%x0=x;
%x1=x; %y1=y;
%y2=y; %x2=x;
}
 P0            | P1            | P2            ;
 MOV R0, #1    | LDR R0, [%x1] | LDR R0, [%y2] ;
 STR R0, [%x0] | MOV R1, #1    | DSB           ;
               | STR R1, [%y1] | LDR R1, [%x2] ;
exists
(1:R0=1 /\ 2:R0=1 /\ 2:R1=0)