Run LB+dmb+addr in model, using armmem
ARM LB+dmb+addr "DMBdRW Rfe DpAddrdW Rfe" Cycle=Rfe DMBdRW Rfe DpAddrdW { %x0=x; %y0=y; %y1=y; %x1=x; } P0 | P1 ; LDR R0, [%x0] | LDR R0, [%y1] ; DMB | EOR R1,R0,R0 ; MOV R1, #1 | MOV R2, #1 ; STR R1, [%y0] | STR R2, [R1,%x1] ; exists (0:R0=1 /\ 1:R0=1)