Test IRIW+ctrl+addr

Run IRIW+ctrl+addr in model, using armmem

ARM IRIW+ctrl+addr
"Rfe DpCtrldR Fre Rfe DpAddrdR Fre"
Cycle=Rfe DpAddrdR Fre Rfe DpCtrldR Fre
{
%x0=x;
%x1=x; %y1=y;
%y2=y;
%y3=y; %x3=x;
}
 P0            | P1            | P2            | P3               ;
 MOV R0, #1    | LDR R0, [%x1] | MOV R0, #1    | LDR R0, [%y3]    ;
 STR R0, [%x0] | CMP R0, R0    | STR R0, [%y2] | EOR R1,R0,R0     ;
               | BNE LC00      |               | LDR R2, [R1,%x3] ;
               | LC00:         |               |                  ;
               | LDR R1, [%y1] |               |                  ;
exists
(1:R0=1 /\ 1:R1=0 /\ 3:R0=1 /\ 3:R2=0)