Test WRC+addrs

Run WRC+addrs in model, using armmem

ARM WRC+addrs
"Rfe DpAddrdW Rfe DpAddrdR Fre"
Cycle=Rfe DpAddrdW Rfe DpAddrdR Fre
{
%x0=x;
%x1=x; %y1=y;
%y2=y; %x2=x;
}
 P0            | P1               | P2               ;
 MOV R0, #1    | LDR R0, [%x1]    | LDR R0, [%y2]    ;
 STR R0, [%x0] | EOR R1,R0,R0     | EOR R1,R0,R0     ;
               | MOV R2, #1       | LDR R2, [R1,%x2] ;
               | STR R2, [R1,%y1] |                  ;
exists
(1:R0=1 /\ 2:R0=1 /\ 2:R2=0)