Test WWC+dmb+po

Run WWC+dmb+po in model, using armmem

ARM WWC+dmb+po
"Rfe DMBdRW Rfe PodRW Wse"
Cycle=Rfe PodRW Wse Rfe DMBdRW
{
%x0=x;
%x1=x; %y1=y;
%y2=y; %x2=x;
}
 P0            | P1            | P2            ;
 MOV R0, #2    | LDR R0, [%x1] | LDR R0, [%y2] ;
 STR R0, [%x0] | DMB           | MOV R1, #1    ;
               | MOV R1, #1    | STR R1, [%x2] ;
               | STR R1, [%y1] |               ;
exists
(x=2 /\ 1:R0=2 /\ 2:R0=1)