Test LB+ctrlisb+po

Run LB+ctrlisb+po in model, using armmem

ARM LB+ctrlisb+po
"DpCtrlIsbdW Rfe PodRW Rfe"
Cycle=Rfe PodRW Rfe DpCtrlIsbdW
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0            | P1            ;
 LDR R0, [%x0] | LDR R0, [%y1] ;
 CMP R0, R0    | MOV R1, #1    ;
 BNE LC00      | STR R1, [%x1] ;
 LC00:         |               ;
 ISB           |               ;
 MOV R1, #1    |               ;
 STR R1, [%y0] |               ;
exists
(0:R0=1 /\ 1:R0=1)