Test LB+dsb+dmb

Run LB+dsb+dmb in model, using armmem

ARM LB+dsb+dmb
"DSBdRW Rfe DMBdRW Rfe"
Cycle=Rfe DMBdRW Rfe DSBdRW
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0            | P1            ;
 LDR R0, [%x0] | LDR R0, [%y1] ;
 DSB           | DMB           ;
 MOV R1, #1    | MOV R1, #1    ;
 STR R1, [%y0] | STR R1, [%x1] ;
exists
(0:R0=1 /\ 1:R0=1)