Disclaimer: All content has been generated automatically by a program running on the titles of publications extracted from people's webpages. Click here for details. ©2007 Advaith Siddharthan
 
Simon Moore
 

Research

(Analysis last run in January 2008)

2005--2007: 'on-chip networks'; 'self-timed circuits'; 'electromagnetic analysis'; 'security evaluation'; 'TFT technology'; 'network-on-chip architectures'; 'improved security characteristics'; 'cryptography implementation'; 'device security enhancement'; 'NOC design'; 'design time'; 'asynchronous PLA'; 'improved input power dynamic range in semiconductor optical amplifier switches'; 'vector co-processor for public key cryptography'; 'computer languages'; 'energy exploration'; 'asynchronous interconnect architecture'; 'vector approach'; 'synchronous systems'; 'multi-wavelength data encoding'; 'hardware-software codesign'; 'pulse-based interconnect'; 'dynamic-logic PLA'; 'intelligent interactive online tutor'; 'timing regime';

2000--2004: 'on-chip networks'; 'self-timed circuits'; 'asynchronous circuits'; 'electromagnetic analysis'; 'security evaluation'; 'smart card applications'; 'hardware stream processing'; 'self-checking asynchronous logic'; 'high precision timing signals'; 'asynchronous control'; 'device security enhancement'; 'multithreaded processor design'; 'statically-allocated languages'; 'embedded systems'; 'asynchronous PLA'; 'self-timed ASIC design'; 'capacitance sensors'; 'multithreaded embedded processors'; 'java-multithreading architecture'; 'optical fault induction attacks'; 'gals interconnect'; 'low-latency virtual-channel routers'; 'point-to-point gals interconnect'; 'three-dimensional visualisation'; 'channel communication'; 'springbank test chip'; 'distributed clock generator'; 'encoded datapaths'; 'stoppable clocks'; 'circuit level defences'; 'simulation methodsology'; 'recalibrated delay line'; 'time-multiplexed autostereoscopic'; 'large-screen autostereoscopic'; 'synchronous subsystems'; 'microprocessor resistant'; 'power analysis attack'; 'security investigations'; 'independent clock domains'; 'ASIC design'; 'asynchronous processors'; 'ROM design';

1995--1999: 'self-timed circuits'; 'asynchronous circuits'; 'multithreaded processor design'; 'self-timed ASIC design'; 'synchronous circuits'; 'rotary pipeline processors'; 'flow table synthesis'; 'geometry planning'; 'tagged up/down sorter'; 'hybrid completion detection'; 'hardware priority queue'; 'asynchronous design'; 'rapid prototyping'; 'frequency locked loops';

1990--1994: 'gas mixture analysis'; 'modified multilayer perceptron models'; 'recursive move machine'; 'predictable memory structures';

Related People
  • Robert Mullins [ CAG ]:
    • 'ASIC design'; 'channel communication'; 'circuit level defences'; 'encoded datapaths'; 'energy exploration'; 'gals interconnect'; 'independent clock domains'; 'optical fault induction attacks'; 'security evaluation'; 'smart card applications'; 'springbank test chip'; 'stoppable clocks'; 'timing regime';
  • Peter Robinson [ Rainbow ]:
    • 'ASIC design'; 'channel communication'; 'embedded self-timed systems'; 'independent clock domains'; 'photonote evaluation'; 'recalibrated delay line'; 'stoppable clocks';
  • Jacques Fournier [ Security ]:
    • 'TFT technology'; 'cryptography implementation'; 'security evaluation'; 'smart card applications'; 'vector approach'; 'vector co-processor for public key cryptography';
  • Ian J Wassell [ DTG ]:
    • 'delay line channel models'; 'evaluation framework'; 'simulation study'; 'time variability'; 'wireless communication';
  • Theo Markettos [ Security ]:
    • 'design time'; 'electromagnetic analysis'; 'security evaluation'; 'simulation methodsology';
  • Athanasios Markettos [ CAG ]:
    • 'design time'; 'electromagnetic analysis'; 'security evaluation'; 'simulation methodsology';
  • Alan Mycroft [ TSG ][ CPRG ][ CAG ]:
    • 'stream processing hardware';