Disclaimer: All content has been generated automatically by a program running on the titles of publications extracted from people's webpages. Click here for details. ©2007 Advaith Siddharthan
 
Robert Mullins
 

Research

(Analysis last run in January 2008)

2005--2007: 'on-chip networks'; 'network-on-chip architectures'; 'energy exploration'; 'synchronous systems'; 'timing regime'; 'dynamic power consumption';

2000--2004: 'on-chip networks'; 'smart card applications'; 'self-timed circuits'; 'asynchronous circuits'; 'security evaluation'; 'self-checking asynchronous logic'; 'gals interconnect'; 'low-latency virtual-channel routers'; 'optical fault induction attacks'; 'point-to-point gals interconnect'; 'springbank test chip'; 'encoded datapaths'; 'independent clock domains'; 'ASIC design'; 'channel communication'; 'stoppable clocks'; 'circuit level defences'; 'synchronous subsystems';

Related People
  • Simon Moore [ Security ][ CAG ]:
    • 'ASIC design'; 'channel communication'; 'circuit level defences'; 'encoded datapaths'; 'energy exploration'; 'gals interconnect'; 'independent clock domains'; 'optical fault induction attacks'; 'security evaluation'; 'smart card applications'; 'springbank test chip'; 'stoppable clocks'; 'timing regime';
  • Peter Robinson [ Rainbow ]:
    • 'ASIC design'; 'channel communication'; 'independent clock domains'; 'photonote evaluation'; 'stoppable clocks';
  • Ian J Wassell [ DTG ]:
    • 'evaluation framework'; 'wireless communication';
  • Peter Sewell [ TSG ]:
    • 'timing {udp}';
  • Ross Anderson [ Security ]:
    • 'optical fault induction attacks'; 'security policy'; 'smart card applications';
  • Min Lin [ DTG ]:
    • 'channel parameters'; 'evaluation framework';
  • Jean Bacon [ SRG ]:
    • 'active security';