Computer Laboratory

Course material 2010–11

System on Chip Design and Modelling

Principal lecturer: Dr David Greaves
Taken by: MPhil ACS

Most of this course will use SystemC TLM2.0 Modelling, but a small amount of Verilog (or VHDL) and PSL will be needed.

Recommended Reading

  • New Book: Transaction-Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems' by Frank Ghenassia. Published Springer 2010.

Primary Course Material

The course has been arranged in four sections and slides will be added in advance of each session.

SECTION 1: Low-level Modelling and Design Refactoring Issues

Section 1: Topics: Verilog RTL Design with examples. Basic RTL to gates synthesis algorithm. Event-driven simulation cycle. Using signals, variables and transactions for component inter-communication. SystemC overview. Hazards, retiming, refactoring. RTL-coding of SoC parts.

Slides 1.1: (RTL design using Verilog/VHDL): Pack 1.1 NB: Many slides are same as vacation pack. Not all slides will be used.

Slides 1.2: (RTL Styles within SystemC): Pack 1.2 NB: Many slides are same as vacation pack.

Slides 1.3: (SoC Parts using RTL-Style Coding): Pack 1.3.

Section 1: Reading List:

SECTION 2: SystemC TLM Modelling & OR1K Hands-on Experiments.

Slides 2.1: (ESL/TLM Modelling): Pack 2.1

Slides 2.2: (Design Partition): Pack 2.2

SECTION 3: High-level Synthesis and Assertion-based Design.

Slides 3.1: (Assertion-Based Design) Pack 3.1

Slides 3.2: (High-Level Synthesis) Pack 3.2

Section 3: Reading List: Not online yet.

SECTION 4: Advanced SoC/NoC Modelling, Power Modelling, Power-Performance Tradeoffs.

Slides 4.1: (Bus NoC Structures) Pack 4.1

Slides 4.2: (Power Control and Modelling) Pack 4.2

Assessed Exercises

The total credit available is 100 marks.

  • Christmas Vacation: An assessed exercise in which two short, illustrative programs in Verilog (or VHDL) and SystemC are created, with hardcopy of the results being submitted (5 Marks, due first day Lent Full Term, Tue 18th Jan '11). FULL DETAILS.

    Vacation slide pack : VACATION READING.

  • Week 3: Short exercises covering basic material: please submit a short written answer to each question. (5 marks total, due week 3, 10:00am Fri 11th Feb '11). Deadline Now extended to Weds 16th Feb. WEEK 3 EXERCISE.

  • Week 5: Ex3: Please submit a portfolio of three modules where a module is a SystemC implementation of a SoC component or else the associated firmware and associated documentation. You must not submit both the hardware and the software modules of the same component. Instead, please collaborate with another group member who will write the other half as part of their portfolio. Please install your module in the shared filespace so that it can be used by any other P35 student. Example components are: Sound or VGA port, DMA controller, Ethernet, Breakpoint/debugger block, DRAM controller, Cache, inter-core message-passing I/F. More details will be provided. Assessed Exercise 3 WEEK 5 EXERCISE. (Credit: 10 marks each, total 30, due week 5+1, 10:00am Friday 4th March '11).

  • Week 7: Ex4: Mini-Project I: A design exercise is completed, based typically on Ex3 work and on papers read in class (10 Marks, due week 7, 10:00 am, Friday 18th March '11 now extended to Friday 25th March). Collaborative work is allowed provided it is made very clear who did what. WEEK 7 EXERCISE.

  • Easter Vacation: Ex5: Mini-Project II and Research Essay: Title 'SoC Design and Modelling' (50 Marks, due first day Easter Full Term, 26th April '11). Collaborating is not allowed for the Research Essay and is only allowed for parts of Mini-Project II that are borrowed from Ex4 or with express permission that will only be granted if the nature of the collaboration will enable individual contributions to be clearly discriminated. Further details are here.

Research Project

The coursework itself contains a lot of practical project work and this is easy to extend in any relevant direction. Alternatively, the modelling tools could be extended in new directions, such as implementing very-high-level simulation or new new logic synthesis algorithm recently reported in the literature. Very-high-level simulation is a new area, where power estimates and other metrics of interest, such as chip area, are obtained from broad-brush design partition decisions without resorting to detailed implementation.

Primary Materials

© David Greaves 2011.