Computer Laboratory

Course material 2010–11

Exercise 1: Michaelmas Vacation Work

Please complete the following work over the Michaelmas Vacation (Dec/Jan 2010/11).

Please submit a printout of source code and console or waveform outputs for Exercise 1a and 1b. Deadline: First day Lent Full Term, Tue 18th Jan '11 (5 Marks).

One half should be done in RTL (Verilog or VHDL) and the other in SystemC.

This exercise is primarily designed to ensure that you are able to run the tools and have no obstacles in your working environment. Please contact D Greaves by email if you have any problem getting started.

Since this is just a preliminary exercise, full marks will be awarded for any reasonable attempt. Also, if any of your answer is not working to your satisfaction at the due deadline a resubmission without loss of credit can be organised.

To get started with the provided tools please look at this TOOLINFO LINK but also please feel free to use any other computers or tools that you have to hand (such as a free copy of Modelsim on your own laptop or a version of SystemC that you have compiled for yourself).

Exercise 1a (Structural Hazard)

If you do Exercise 1a in Verilog (or VHDL) then please do Exercise 1b using SystemC and vice versa.

By 'component' we mean a SystemC 'SC_MODULE' or a Verilog 'module' or a VHDL 'entity'.

  • Write a component called FIB that initialises the first two locations of an array called FA with the numbers 1 and 2 and then iterates through the array computing
    FA[i] := FA[i-1] + FA[i-2]
    and which also generates some sort of output so that we know it worked.

  • Create a component called RAM that contains several addressable locations inside it. The interface to the component should have the property that only one internal location can be addressed at a time.

  • Modify your FIB module to become FIBRAM so that it connects to your RAM model (either externally or by instantiating it) and uses this instead of the array called FA.

  • Read up about structural hazards from a textbook or the Internet and make a brief comment or two.

Exercise 1b (M/D/1 Queue)

If you did Exercise 1a in Verilog (or VHDL) then please do this one using SystemC.

In this exercise you must decide how to model a 'packet' at some reasonable level of abstraction. A packet must contain an originating timestamp and perhaps some other information such as an incrementing counter value that resembles data.

You must also decide how to model an interface that can carry these packets. You can use shared variables to model wires (as is common in RTL) or you might use subroutine calling over the interface.

  • Create a component called generator that generates randomly spaced packets on an output interface. The component should have inside it a parameter called lambda that controls the average rate of traffic generation in terms of events per second. (Using your own PRBS may be the easiest source of random numbers in RTL.)

  • Create a component called sink that accepts packets and which goes busy for some constant time set by an internal parameter called mu before it is ready to accept the next event. The sink must report somehow the transit time experienced by the packets (i.e. subtract the current time from the originating timestamp).

  • Create a component called fifoqueue suitable to be wired between the generator and the sink.

  • Run the system several times with different relative settings of lambda and mu and compute the average of the transit delays. Search for 'M/D/1' queue on the Internet or in a queuing theory book and see if you can make any observations.

© David Greaves 2011.