Simon Moore

News

• October 2024 - presentations and posters were presented by us and others on CHERI at the RISC-V Summit north America 2024. In particular, Carl Shaw from Codasip presented work on Demonstrated CHERI enhanced Linux mitigating buffer overflow attacks.
• August 2024 - new publication: A Suite of Processors to Explore CHERI-RISC-V Micro Architecture, 2024 27th Euromicro Conference on Digital System Design (DSD), Paris, France, 2024, pp. 351-360, IEEE DOI.
• June 2024 - We presented our CHERI-RISC-V core at the RISC-V Summit Europe 2024. YouTube Video
• June 2024 - Launch of the Computer Architecture Group Research Centre. Website
• June 2024 - I hosted lowRISC's Sunburst Hackathon - CHERIoT on a custom FPGA board. Article
• May 2024 - New DSIT report on our CHERI technology: CHERI adoption and diffusion research
• April 2024 - New paper: Cornucopia Reloaded: Load Barriers for CHERI Heap Temporal Safety
• April 2024 - CHERITech24 workshop in Cambridge. Great to see over 140 deligates from industry, academia and government exploring CHERI security technology. Slides and videos are now available.
• February 2024 - The White House press release on Future Software Should be Memory Safe recommend our work on the CHERI security model in the accompanying technical report: Back to Building Blocks: A Path Toward Secure and Measurable Software.
• November 2023 - I spoke at the UK-US Semiconductor Security Workshop: Security in the Era of Global Semiconductor Initiatives in Washington DC. Slides: PDF
• August 2023 - New PhD thesis released: Efficient spatial and temporal safety for microcontrollers and application-class processors
• June 2023 - ISCA@50 Retrospective recognises our work from 2004 on Low-Latency Virtual-Channel Routers for On-Chip Networks - see the Retrospective Article
• June 2023 - Speaking at the Leti Innovation Days event in the Cyber Security track.
• May 2023 - CHERI is part of the UK National Semiconductor Strategy.
• April 2023 - CHERI recommended as the secure hardware foundation in the intergovernmental report Shifting the Balance of Cybersecurity Risk: Principles and Approaches for Security-by Design and -Default
• March 2023 - CHERITech23 in Glasgow. I gave the keynote. Link to workshop details includeing slides.
• March 2023 - New Ph.D. thesis as a technical report: Protecting enclaves from side-channel attacks through physical isolation by Marno van der Maas
• February 2023 - Microsoft announces CHERIoT: Rethinking security for low-cost embedded systems that includes a reference hardware implementation and software stack including an RTOS.
• January 2023 - HotChips 2022 presentation on our work with Arm is released: Arm Morello Evaluation Platform - Validating CHERI-based Security in a High-performance System - YouTube and Slides in PDF
• October 2022 - Our CHERI work was one of the finalists for the Royal Academy of Engineering Bhattacharyya Award. See the YouTube video
• September 2022 - Microsoft announce a production-ready CHERI-enabled Ibex microcontroller
• September 2022 - CHERITech22 workshop at King's College London brings together academics and industrialists exploring and using our CHERI secure processor technology
• May 2022 - CHERI Session at RISC-V Week in Paris
• March 2022 - YouTube video about CHERI from Digital Security by Design event
• October 2020 - Microsoft Security Response Centre have released an analysis of our CHERI hardware/software stack showing the many benefits of our technology: PDF on GitHub
• October 2020 - CHERI-ARM prototype architecture (Morello) announced: https://developer.arm.com/architectures/cpu-architecture/a-profile/morello
• Sept 2020 - CHERI-RISC-V talk presented at Texas A&M. Video is here.
• May 2020 - More CHERI advances presented at Oakland (IEEE Security & Privacy Conference): Cornucopia: Temporal Safety for CHERI Heaps and Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process
• October 2019 - ARM to build a prototype ARM SoC with our CHERI technology - press releases: UK Gov, Cambridge, The Register and our CHERI project page. Talk by Richard Grisenthwaite, Chief Architect at ARM
• October 2019 - MICRO paper: CHERIvoke: Characterising Pointer Revocation using CHERI Capabilities for Temporal Memory Safety PDF, YouTube lightning talk
• September 2019 - FPL paper: Tinsel: a manythread overlay for FPGA clusters. [Open Access]
• May 2019 - IEEE Transactions on Computers paper: CHERI Concentrate: Practical Compressed Capabilities. [IEEExplore] [PDF]
• April 2019 - award winning ASPLOS'19 paper: CheriABI: Enforcing Valid Pointer Provenance and Minimizing Pointer Privilege in the POSIX C Run-time Environment., [PDF], [Brief intro. on YouTube]
• February 2019 - NDSS'19 paper: Thunderclap: Exploring Vulnerabilities in Operating System IOMMU Protection via DMA from Untrustworthy Peripherals. [PDF], [Website], Press: The Register, ZDNet, Tom's hardware and guide, The Verge, Apple Insider, MS Power User, Beeping Computer, Threat Post, cyberscoop, TechTalkThai, Economic Times (India), Press release, Blog
• February 2019 - ASPLOS'19 paper: CheriABI: Enforcing Valid Pointer Provenance and Minimizing Pointer Privilege in the POSIX C Run-time Environment.[PDF]
• January 2019 - Arm announce that that have been working with us to add CHERI protections to Arm processors.
• August 2018 - The New Scientist has published an article, Uncrackable computer chips stop malicious bugs attacking your computer, covering CHERI and other projects relating to security-focused computer architectures.
• April 2018 - Dr Colin Rothwell graduates for his PhD work on Protection from malicious peripherals (thesis to be released soon)
• March 2018 - Talk at the RISE (Research Institute for Secure Hardware and Embedded Systems) spring school at Trinity Hall - an update of Winning the War in Memory Programme and [YouTube Video]. There is also a follow-on talk from Dr Watson on CHERI - Architecture support for memory protection and compartmentalisation [YouTube Video]
• February 2018 - [Technical report] on Capability Hardware Enhanced RISC Instructions (CHERI): Notes on the Meltdown and Spectre Attacks
• November 2017 - Paper on Efficient Tagged Memory at the IEEE ICCD conference [PDF]
• September 2017 - Talk at ARM Research Summit - Winning the War in Memory - [YouTube Video] and follow-on talk on CheriABI from Dr Robert Watson [YouTube Video]
• April 2017 - Paper at ASPLOS 2017 - CHERI JNI: Sinking the Java security model into the C: [Open Access Archive]
• October 2016 - IEEE Micro paper on Fast Protection-Domain Crossing in the CHERI Capability-System Architecture: [IEEE DOI: 10.1109/MM.2016.84, Open Access Archive]
• October 2016 - FMCAD paper on A Consistency Checker for Memory Subsystem Traces [PDF]
• January 2016 - ten year retrospective award at ASP-DAC for the most influential paper, for work on low-latency on-chip networks see news article.
• May 2015 - paper on CHERI: A Hybrid Capability-System Architecture for Scalable Software Compartmentalization presented at IEEE Security and Privacy.
• March 2015 - paper on Beyond the PDP-11: Processor support for a memory-safe C abstract machine won best presentation prize at ASPLOS 2015. Won the audience picks: best presentation award (well done to David Chisnall who presented our paper)
• October 2014 - promoted to Professor of Computer Engineering.
• September 2014 - 21st Ph.D. student submits his thesis: Steven Marsh on Efficient programming models for neurocomputation.
• September 2014 - two papers presented at FPL on vector compute and FPGA-to-FPGA communication - see publications list
• July 2014 - Celebrating 2⁴ years as a faculty member.
• July 2014 - 20th Ph.D. student graduates: Jonathan Woodruff's thesis on CHERI: A RISC capability machine for practical memory safety
• June 2014 - The CHERI capability model: Revisiting RISC in an age of risk presented at ISCA: Video and PDF paper
• December 2013 - Video of tadpole neural model on FPGA
• September 2013 - Paper presented at FPL comparing custom computing to vector processing
• June 2013 - FPGA prototype tablet design open sourced based around a DE4 board and multitouch screen
• May 2013 - PCIe-to-SATA breakout board open sourced
• March 2013 - Video of Nengo character recognition system on FPGA
• March 2013 - Paul Fox's thesis on Massively Parallel Neural Computation
• February 2013 - Philip Paul's thesis on Microelectronic Security Measures
• January 2013 - Rosemary Fancis' Ph.D. thesis on Exploring NoCs for FPGAs
• September 2012 - Paper on Mamba - A Scalable Communication Centric Multithreaded Processor Architecture appears at ICCD
• July 2012 - Advertising two RA/SRA positions (now closed)
• July 2012 - paper on Energy Implications of Photonic Networks With Speculative Transmission highlighted by OCN Journal
• July 2012 - keynote on Communication - the next resource war at ReCoSoC 2012.
• June 2012 - paper on Energy Implications of Photonic Networks With Speculative Transmission is spotlighted by OCN
• June 2012 - paper on Asynchronous Remote Stores for Inter-Processor Communication at FASPP2012
• April 2012 - Initial results from Bluehive (massively parallel FPGA platform) appear at FCCM 2012
• March 2012 - Our CHERI processor boots multiuser FreeBSD on FPGA
• March 2012 - paper CHERI: a research platform deconflating hardware virtualization and protection at RESoLVE 2012
• Feb 2012 - Designing a physical locality aware coherence protocol for CMPs accepted by IEEE Transactions on Computers
• Nov 2011 - Dan Greenfield wins the 2011 distinguished dissertation award
• Oct 2011 - Large grant awarded under the DARPA Mission Oriented Resilient Clouds program
• June 2010 - awarded the Pilkington Teaching Prize