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00034 #if !defined(__DWC_CIL_H__)
00035 #define __DWC_CIL_H__
00036
00037 #include "dwc_os.h"
00038 #include "dwc_list.h"
00039 #include "dwc_otg_dbg.h"
00040 #include "dwc_otg_regs.h"
00041
00042 #include "dwc_otg_core_if.h"
00043
00049 #ifdef DWC_UTE_CFI
00050
00051 #define MAX_DMA_DESCS_PER_EP 256
00052
00056 typedef enum _data_buffer_mode {
00057 BM_STANDARD = 0,
00058 BM_SG = 1,
00059 BM_CONCAT = 2,
00060 BM_CIRCULAR = 3,
00061 BM_ALIGN = 4
00062 } data_buffer_mode_e;
00063 #endif //DWC_UTE_CFI
00064
00067 #define OTG_CORE_REV_2_60a 0x4F54260A
00068 #define OTG_CORE_REV_2_71a 0x4F54271A
00069 #define OTG_CORE_REV_2_72a 0x4F54272A
00070 #define OTG_CORE_REV_2_80a 0x4F54280A
00071 #define OTG_CORE_REV_2_81a 0x4F54281A
00072 #define OTG_CORE_REV_2_90a 0x4F54290A
00073
00077 typedef struct iso_pkt_info {
00078 uint32_t offset;
00079 uint32_t length;
00080 int32_t status;
00081 } iso_pkt_info_t;
00082
00088 typedef struct dwc_ep {
00090 uint8_t num;
00092 unsigned is_in:1;
00094 unsigned active:1;
00095
00098 unsigned tx_fifo_num:4;
00100 unsigned type:2;
00101 #define DWC_OTG_EP_TYPE_CONTROL 0
00102 #define DWC_OTG_EP_TYPE_ISOC 1
00103 #define DWC_OTG_EP_TYPE_BULK 2
00104 #define DWC_OTG_EP_TYPE_INTR 3
00105
00107 unsigned data_pid_start:1;
00109 unsigned even_odd_frame:1;
00111 unsigned maxpacket:11;
00112
00114 uint32_t maxxfer;
00115
00124 dwc_dma_t dma_addr;
00125
00126 dwc_dma_t dma_desc_addr;
00127 dwc_otg_dev_dma_desc_t *desc_addr;
00128
00129 uint8_t *start_xfer_buff;
00131 uint8_t *xfer_buff;
00133 unsigned xfer_len:19;
00135 unsigned xfer_count:19;
00137 unsigned sent_zlp:1;
00139 unsigned total_len:19;
00140
00142 unsigned stall_clear_flag:1;
00143
00144 #ifdef DWC_UTE_CFI
00145
00146 data_buffer_mode_e buff_mode;
00147
00148
00149
00150
00151 dwc_otg_dma_desc_t *descs;
00152
00153
00154 dma_addr_t descs_dma_addr;
00156 uint32_t cfi_req_len;
00157 #endif //DWC_UTE_CFI
00158
00160 uint32_t desc_cnt;
00161
00162 #ifdef DWC_EN_ISOC
00163
00168 dwc_dma_t dma_addr0;
00169 dwc_dma_t dma_addr1;
00170
00171 dwc_dma_t iso_dma_desc_addr;
00172 dwc_otg_dev_dma_desc_t *iso_desc_addr;
00173
00175 uint8_t *xfer_buff0;
00176 uint8_t *xfer_buff1;
00177
00179 uint32_t proc_buf_num;
00181 uint32_t buf_proc_intrvl;
00183 uint32_t data_per_frame;
00184
00185
00187 uint32_t data_pattern_frame;
00189 uint32_t sync_frame;
00190
00192 uint32_t bInterval;
00194 uint32_t pkt_per_frm;
00196 uint32_t next_frame;
00198 uint32_t pkt_cnt;
00200 iso_pkt_info_t *pkt_info;
00202 uint32_t cur_pkt;
00204 uint8_t *cur_pkt_addr;
00206 uint32_t cur_pkt_dma_addr;
00207 #endif
00208
00210 } dwc_ep_t;
00211
00212
00213
00214
00215 typedef enum dwc_otg_halt_status {
00216 DWC_OTG_HC_XFER_NO_HALT_STATUS,
00217 DWC_OTG_HC_XFER_COMPLETE,
00218 DWC_OTG_HC_XFER_URB_COMPLETE,
00219 DWC_OTG_HC_XFER_ACK,
00220 DWC_OTG_HC_XFER_NAK,
00221 DWC_OTG_HC_XFER_NYET,
00222 DWC_OTG_HC_XFER_STALL,
00223 DWC_OTG_HC_XFER_XACT_ERR,
00224 DWC_OTG_HC_XFER_FRAME_OVERRUN,
00225 DWC_OTG_HC_XFER_BABBLE_ERR,
00226 DWC_OTG_HC_XFER_DATA_TOGGLE_ERR,
00227 DWC_OTG_HC_XFER_AHB_ERR,
00228 DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,
00229 DWC_OTG_HC_XFER_URB_DEQUEUE
00230 } dwc_otg_halt_status_e;
00231
00237 typedef struct dwc_hc {
00239 uint8_t hc_num;
00240
00242 unsigned dev_addr:7;
00243
00245 unsigned ep_num:4;
00246
00248 unsigned ep_is_in:1;
00249
00257 unsigned speed:2;
00258 #define DWC_OTG_EP_SPEED_LOW 0
00259 #define DWC_OTG_EP_SPEED_FULL 1
00260 #define DWC_OTG_EP_SPEED_HIGH 2
00261
00270 unsigned ep_type:2;
00271
00273 unsigned max_packet:11;
00274
00283 unsigned data_pid_start:2;
00284 #define DWC_OTG_HC_PID_DATA0 0
00285 #define DWC_OTG_HC_PID_DATA2 1
00286 #define DWC_OTG_HC_PID_DATA1 2
00287 #define DWC_OTG_HC_PID_MDATA 3
00288 #define DWC_OTG_HC_PID_SETUP 3
00289
00291 unsigned multi_count:2;
00292
00297 uint8_t *xfer_buff;
00302 dwc_dma_t align_buff;
00304 uint32_t xfer_len;
00306 uint32_t xfer_count;
00308 uint16_t start_pkt_count;
00309
00314 uint8_t xfer_started;
00315
00320 uint8_t do_ping;
00321
00326 uint8_t error_state;
00327
00334 uint8_t halt_on_queue;
00335
00340 uint8_t halt_pending;
00341
00345 dwc_otg_halt_status_e halt_status;
00346
00347
00348
00349
00350 uint8_t do_split;
00351 uint8_t complete_split;
00352 uint8_t hub_addr;
00354 uint8_t port_addr;
00361 uint8_t xact_pos;
00362
00364 uint8_t short_read;
00365
00370 uint8_t requests;
00371
00375 struct dwc_otg_qh *qh;
00376
00380 DWC_CIRCLEQ_ENTRY(dwc_hc) hc_list_entry;
00381
00386 uint16_t ntd;
00387
00389 dwc_dma_t desc_list_addr;
00390
00392 uint8_t schinfo;
00393
00395 } dwc_hc_t;
00396
00401 typedef struct dwc_otg_core_params {
00402 int32_t opt;
00403
00411 int32_t otg_cap;
00412
00420 int32_t dma_enable;
00421
00429 int32_t dma_desc_enable;
00433 int32_t dma_burst_size;
00434
00443 int32_t speed;
00449 int32_t host_support_fs_ls_low_power;
00450
00459 int32_t host_ls_low_power_phy_clk;
00460
00465 int32_t enable_dynamic_fifo;
00466
00473 int32_t data_fifo_size;
00474
00479 int32_t dev_rx_fifo_size;
00480
00485 int32_t dev_nperio_tx_fifo_size;
00486
00491 uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
00492
00497 int32_t host_rx_fifo_size;
00498
00503 int32_t host_nperio_tx_fifo_size;
00504
00509 int32_t host_perio_tx_fifo_size;
00510
00514 int32_t max_transfer_size;
00515
00519 int32_t max_packet_count;
00520
00525 int32_t host_channels;
00526
00533 int32_t dev_endpoints;
00534
00543 int32_t phy_type;
00544
00556 int32_t phy_utmi_width;
00557
00568 int32_t phy_ulpi_ddr;
00569
00574 int32_t phy_ulpi_ext_vbus;
00575
00582 int32_t i2c_enable;
00583
00584 int32_t ulpi_fs_ls;
00585
00586 int32_t ts_dline;
00587
00594 int32_t en_multiple_tx_fifo;
00595
00600 uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
00601
00607 uint32_t thr_ctl;
00608
00612 uint32_t tx_thr_length;
00613
00617 uint32_t rx_thr_length;
00618
00622 int32_t lpm_enable;
00623
00629 int32_t pti_enable;
00630
00636 int32_t mpi_enable;
00637
00642 int32_t ic_usb_cap;
00643
00650 int32_t ahb_thr_ratio;
00651
00652 } dwc_otg_core_params_t;
00653
00654 #ifdef DEBUG
00655 struct dwc_otg_core_if;
00656 typedef struct hc_xfer_info {
00657 struct dwc_otg_core_if *core_if;
00658 dwc_hc_t *hc;
00659 } hc_xfer_info_t;
00660 #endif
00661
00662
00663
00664 typedef enum dwc_otg_lx_state {
00666 DWC_OTG_L0,
00668 DWC_OTG_L1,
00670 DWC_OTG_L2,
00672 DWC_OTG_L3
00673 } dwc_otg_lx_state_e;
00674
00680 struct dwc_otg_core_if {
00682 dwc_otg_core_params_t *core_params;
00683
00685 dwc_otg_core_global_regs_t *core_global_regs;
00686
00688 dwc_otg_dev_if_t *dev_if;
00690 dwc_otg_host_if_t *host_if;
00691
00693 uint32_t snpsid;
00694
00695
00696
00697
00698
00699 uint8_t phy_init_done;
00700
00701
00702
00703
00704 uint8_t srp_success;
00705 uint8_t srp_timer_started;
00706
00707
00709 volatile uint32_t *pcgcctl;
00710 #define DWC_OTG_PCGCCTL_OFFSET 0xE00
00711
00713 uint32_t *data_fifo[MAX_EPS_CHANNELS];
00714 #define DWC_OTG_DATA_FIFO_OFFSET 0x1000
00715 #define DWC_OTG_DATA_FIFO_SIZE 0x1000
00716
00718 uint16_t total_fifo_size;
00720 uint16_t rx_fifo_size;
00722 uint16_t nperio_tx_fifo_size;
00723
00725 uint8_t dma_enable;
00726
00728 uint8_t dma_desc_enable;
00729
00731 uint8_t pti_enh_enable;
00732
00734 uint8_t multiproc_int_enable;
00735
00737 uint8_t en_multiple_tx_fifo;
00738
00741 uint8_t queuing_high_bandwidth;
00742
00744 hwcfg1_data_t hwcfg1;
00745 hwcfg2_data_t hwcfg2;
00746 hwcfg3_data_t hwcfg3;
00747 hwcfg4_data_t hwcfg4;
00748
00750 hcfg_data_t hcfg;
00751 dcfg_data_t dcfg;
00752
00758 uint8_t op_state;
00759
00765 uint8_t restart_hcd_on_session_req;
00766
00769 #define A_HOST (1)
00770
00771 #define A_SUSPEND (2)
00772
00773 #define A_PERIPHERAL (3)
00774
00775 #define B_PERIPHERAL (4)
00776
00777 #define B_HOST (5)
00778
00780 struct dwc_otg_cil_callbacks *hcd_cb;
00782 struct dwc_otg_cil_callbacks *pcd_cb;
00783
00785 uint32_t p_tx_msk;
00787 uint32_t tx_msk;
00788
00790 dwc_workq_t *wq_otg;
00791
00793 dwc_timer_t *wkp_timer;
00794
00795 #ifdef DEBUG
00796 uint32_t start_hcchar_val[MAX_EPS_CHANNELS];
00797
00798 hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS];
00799 dwc_timer_t *hc_xfer_timer[MAX_EPS_CHANNELS];
00800
00801 uint32_t hfnum_7_samples;
00802 uint64_t hfnum_7_frrem_accum;
00803 uint32_t hfnum_0_samples;
00804 uint64_t hfnum_0_frrem_accum;
00805 uint32_t hfnum_other_samples;
00806 uint64_t hfnum_other_frrem_accum;
00807 #endif
00808
00809 #ifdef DWC_UTE_CFI
00810 uint16_t pwron_rxfsiz;
00811 uint16_t pwron_gnptxfsiz;
00812 uint16_t pwron_txfsiz[15];
00813
00814 uint16_t init_rxfsiz;
00815 uint16_t init_gnptxfsiz;
00816 uint16_t init_txfsiz[15];
00817 #endif
00818
00820 dwc_otg_lx_state_e lx_state;
00821
00822 };
00823
00824 #ifdef DEBUG
00825
00826
00827
00828 extern void hc_xfer_timeout(void *ptr);
00829 #endif
00830
00831
00832
00833
00834
00835 extern void w_conn_id_status_change(void *p);
00836
00837 extern void w_wakeup_detected(void *p);
00838
00839
00840
00841
00842
00843 extern void dwc_otg_core_host_init(dwc_otg_core_if_t * _core_if);
00844 extern void dwc_otg_core_dev_init(dwc_otg_core_if_t * _core_if);
00845
00851 extern void dwc_otg_wakeup(dwc_otg_core_if_t * _core_if);
00852 extern void dwc_otg_read_setup_packet(dwc_otg_core_if_t * _core_if,
00853 uint32_t * _dest);
00854 extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * _core_if);
00855 extern void dwc_otg_ep0_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
00856 extern void dwc_otg_ep_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
00857 extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
00858 extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * _core_if,
00859 dwc_ep_t * _ep);
00860 extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * _core_if,
00861 dwc_ep_t * _ep);
00862 extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * _core_if,
00863 dwc_ep_t * _ep);
00864 extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * _core_if,
00865 dwc_ep_t * _ep);
00866 extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t * _core_if,
00867 dwc_ep_t * _ep, int _dma);
00868 extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
00869 extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * _core_if,
00870 dwc_ep_t * _ep);
00871 extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * _core_if);
00872
00873 #ifdef DWC_EN_ISOC
00874 extern void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,
00875 dwc_ep_t * ep);
00876 extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if,
00877 dwc_ep_t * ep);
00878 #endif
00879
00886 extern void dwc_otg_hc_init(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
00887 extern void dwc_otg_hc_halt(dwc_otg_core_if_t * _core_if,
00888 dwc_hc_t * _hc, dwc_otg_halt_status_e _halt_status);
00889 extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
00890 extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * _core_if,
00891 dwc_hc_t * _hc);
00892 extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * _core_if,
00893 dwc_hc_t * _hc);
00894 extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
00895 extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t * _core_if,
00896 dwc_hc_t * _hc);
00897 extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * _core_if);
00898 extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * _core_if);
00899
00900 extern void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if, dwc_hc_t * hc);
00901
00902
00903 #define clear_hc_int(_hc_regs_, _intr_) \
00904 do { \
00905 hcint_data_t hcint_clear = {.d32 = 0}; \
00906 hcint_clear.b._intr_ = 1; \
00907 dwc_write_reg32(&(_hc_regs_)->hcint, hcint_clear.d32); \
00908 } while (0)
00909
00910
00911
00912
00913
00914
00915
00916
00917 #define disable_hc_int(_hc_regs_, _intr_) \
00918 do { \
00919 hcintmsk_data_t hcintmsk = {.d32 = 0}; \
00920 hcintmsk.b._intr_ = 1; \
00921 dwc_modify_reg32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \
00922 } while (0)
00923
00929 static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t * _core_if)
00930 {
00931 hprt0_data_t hprt0;
00932 hprt0.d32 = dwc_read_reg32(_core_if->host_if->hprt0);
00933 hprt0.b.prtena = 0;
00934 hprt0.b.prtconndet = 0;
00935 hprt0.b.prtenchng = 0;
00936 hprt0.b.prtovrcurrchng = 0;
00937 return hprt0.d32;
00938 }
00939
00948 extern void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
00949 uint8_t * dest, uint16_t bytes);
00950
00951 extern void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * _core_if, const int _num);
00952 extern void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * _core_if);
00953 extern void dwc_otg_core_reset(dwc_otg_core_if_t * _core_if);
00954
00958 static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t * core_if)
00959 {
00960 return (dwc_read_reg32(&core_if->core_global_regs->gintsts) &
00961 dwc_read_reg32(&core_if->core_global_regs->gintmsk));
00962 }
00963
00967 static inline uint32_t dwc_otg_read_otg_intr(dwc_otg_core_if_t * core_if)
00968 {
00969 return (dwc_read_reg32(&core_if->core_global_regs->gotgint));
00970 }
00971
00976 static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *
00977 core_if)
00978 {
00979
00980 uint32_t v;
00981
00982 if (core_if->multiproc_int_enable) {
00983 v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->
00984 deachint) & dwc_read_reg32(&core_if->dev_if->
00985 dev_global_regs->
00986 deachintmsk);
00987 } else {
00988 v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->daint) &
00989 dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk);
00990 }
00991 return (v & 0xffff);
00992 }
00993
00998 static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *
00999 core_if)
01000 {
01001 uint32_t v;
01002
01003 if (core_if->multiproc_int_enable) {
01004 v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->
01005 deachint) & dwc_read_reg32(&core_if->dev_if->
01006 dev_global_regs->
01007 deachintmsk);
01008 } else {
01009 v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->daint) &
01010 dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk);
01011 }
01012
01013 return ((v & 0xffff0000) >> 16);
01014 }
01015
01019 static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t * core_if,
01020 dwc_ep_t * ep)
01021 {
01022 dwc_otg_dev_if_t *dev_if = core_if->dev_if;
01023 uint32_t v, msk, emp;
01024
01025 if (core_if->multiproc_int_enable) {
01026 msk =
01027 dwc_read_reg32(&dev_if->dev_global_regs->
01028 diepeachintmsk[ep->num]);
01029 emp =
01030 dwc_read_reg32(&dev_if->dev_global_regs->
01031 dtknqr4_fifoemptymsk);
01032 msk |= ((emp >> ep->num) & 0x1) << 7;
01033 v = dwc_read_reg32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
01034 } else {
01035 msk = dwc_read_reg32(&dev_if->dev_global_regs->diepmsk);
01036 emp =
01037 dwc_read_reg32(&dev_if->dev_global_regs->
01038 dtknqr4_fifoemptymsk);
01039 msk |= ((emp >> ep->num) & 0x1) << 7;
01040 v = dwc_read_reg32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
01041 }
01042
01043 return v;
01044 }
01045
01049 static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *
01050 _core_if, dwc_ep_t * _ep)
01051 {
01052 dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
01053 uint32_t v;
01054 doepmsk_data_t msk = {.d32 = 0 };
01055
01056 if (_core_if->multiproc_int_enable) {
01057 msk.d32 =
01058 dwc_read_reg32(&dev_if->dev_global_regs->
01059 doepeachintmsk[_ep->num]);
01060 if (_core_if->pti_enh_enable) {
01061 msk.b.pktdrpsts = 1;
01062 }
01063 v = dwc_read_reg32(&dev_if->out_ep_regs[_ep->num]->
01064 doepint) & msk.d32;
01065 } else {
01066 msk.d32 = dwc_read_reg32(&dev_if->dev_global_regs->doepmsk);
01067 if (_core_if->pti_enh_enable) {
01068 msk.b.pktdrpsts = 1;
01069 }
01070 v = dwc_read_reg32(&dev_if->out_ep_regs[_ep->num]->
01071 doepint) & msk.d32;
01072 }
01073 return v;
01074 }
01075
01079 static inline uint32_t dwc_otg_read_host_all_channels_intr(dwc_otg_core_if_t *
01080 _core_if)
01081 {
01082 return (dwc_read_reg32(&_core_if->host_if->host_global_regs->haint));
01083 }
01084
01085 static inline uint32_t dwc_otg_read_host_channel_intr(dwc_otg_core_if_t *
01086 _core_if, dwc_hc_t * _hc)
01087 {
01088 return (dwc_read_reg32
01089 (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint));
01090 }
01091
01097 static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t * _core_if)
01098 {
01099 return (dwc_read_reg32(&_core_if->core_global_regs->gintsts) & 0x1);
01100 }
01101
01109 typedef struct dwc_otg_cil_callbacks {
01111 int (*start) (void *_p);
01113 int (*stop) (void *_p);
01115 int (*disconnect) (void *_p);
01117 int (*resume_wakeup) (void *_p);
01119 int (*suspend) (void *_p);
01121 int (*session_start) (void *_p);
01122 #ifdef CONFIG_USB_DWC_OTG_LPM
01123
01124 int (*sleep) (void *_p);
01125 #endif
01126
01127 void *p;
01128 } dwc_otg_cil_callbacks_t;
01129
01130 extern void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * _core_if,
01131 dwc_otg_cil_callbacks_t * _cb,
01132 void *_p);
01133 extern void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * _core_if,
01134 dwc_otg_cil_callbacks_t * _cb,
01135 void *_p);
01136
01137 #endif