dwc_ep structure represents the state of a single endpoint when acting in device mode.
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#include <dwc_otg_cil.h>
Data Fields | |
| uint8_t | num |
| EP number used for register address lookup. | |
| unsigned | is_in:1 |
| EP direction 0 = OUT. | |
| unsigned | active:1 |
| EP active. | |
| unsigned | tx_fifo_num:4 |
| Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic Tx FIFO If dedicated Tx FIFOs are enabled for all IN Eps - Tx FIFO # FOR IN EPs. | |
| unsigned | type:2 |
| EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR. | |
| unsigned | data_pid_start:1 |
| DATA start PID for INTR and BULK EP. | |
| unsigned | even_odd_frame:1 |
| Frame (even/odd) for ISOC EP. | |
| unsigned | maxpacket:11 |
| Max Packet bytes. | |
| uint32_t | maxxfer |
| Max Transfer size. | |
Transfer state | |
| dwc_dma_t | dma_addr |
| Pointer to the beginning of the transfer buffer -- do not modify during transfer. | |
| dwc_dma_t | dma_desc_addr |
| dwc_otg_dev_dma_desc_t * | desc_addr |
| uint8_t * | start_xfer_buff |
| uint8_t * | xfer_buff |
| pointer to the transfer buffer | |
| unsigned | xfer_len:19 |
| Number of bytes to transfer. | |
| unsigned | xfer_count:19 |
| Number of bytes transferred. | |
| unsigned | sent_zlp:1 |
| Sent ZLP. | |
| unsigned | total_len:19 |
| Total len for control transfer. | |
| unsigned | stall_clear_flag:1 |
| stall clear flag | |
| uint32_t | desc_cnt |
| Allocated DMA Desc count. | |
| dwc_dma_t | dma_addr0 |
| DMA addresses of ISOC buffers. | |
| dwc_dma_t | dma_addr1 |
| dwc_dma_t | iso_dma_desc_addr |
| dwc_otg_dev_dma_desc_t * | iso_desc_addr |
| uint8_t * | xfer_buff0 |
| pointer to the transfer buffers | |
| uint8_t * | xfer_buff1 |
| uint32_t | proc_buf_num |
| number of ISOC Buffer is processing | |
| uint32_t | buf_proc_intrvl |
| Interval of ISOC Buffer processing. | |
| uint32_t | data_per_frame |
| Data size for regular frame. | |
| uint32_t | data_pattern_frame |
| Data size for pattern frame. | |
| uint32_t | sync_frame |
| Frame number of pattern data. | |
| uint32_t | bInterval |
| bInterval | |
| uint32_t | pkt_per_frm |
| ISO Packet number per frame. | |
| uint32_t | next_frame |
| Next frame num for which will be setup DMA Desc. | |
| uint32_t | pkt_cnt |
| Number of packets per buffer processing. | |
| iso_pkt_info_t * | pkt_info |
| Info for all isoc packets. | |
| uint32_t | cur_pkt |
| current pkt number | |
| uint8_t * | cur_pkt_addr |
| current pkt number | |
| uint32_t | cur_pkt_dma_addr |
| current pkt number | |
dwc_ep structure represents the state of a single endpoint when acting in device mode.
It contains the data items needed for an endpoint to be activated and transfer packets.
Definition at line 88 of file dwc_otg_cil.h.
1.4.7