dwc_otg_cil.c File Reference

The Core Interface Layer provides basic services for accessing and managing the DWC_otg hardware. More...

#include "dwc_os.h"
#include "dwc_otg_regs.h"
#include "dwc_otg_cil.h"

Go to the source code of this file.

Defines

#define DWC_OTG_PARAM_TEST(_param_, _low_, _high_)

Functions

static int dwc_otg_setup_params (dwc_otg_core_if_t *core_if)
dwc_otg_core_if_t * dwc_otg_cil_init (const uint32_t *reg_base_addr)
 This function is called to initialize the DWC_otg CSR data structures.
void dwc_otg_cil_remove (dwc_otg_core_if_t *core_if)
 This function frees the structures allocated by dwc_otg_cil_init().
void dwc_otg_enable_global_interrupts (dwc_otg_core_if_t *core_if)
 This function enables the controller's Global Interrupt in the AHB Config register.
void dwc_otg_disable_global_interrupts (dwc_otg_core_if_t *core_if)
 This function disables the controller's Global Interrupt in the AHB Config register.
static void dwc_otg_enable_common_interrupts (dwc_otg_core_if_t *core_if)
 This function initializes the commmon interrupts, used in both device and host modes.
static void init_fslspclksel (dwc_otg_core_if_t *core_if)
 Initializes the FSLSPClkSel field of the HCFG register depending on the PHY type.
static void init_devspd (dwc_otg_core_if_t *core_if)
 Initializes the DevSpd field of the DCFG register depending on the PHY type and the enumeration speed of the device.
static uint32_t calc_num_in_eps (dwc_otg_core_if_t *core_if)
 This function calculates the number of IN EPS using GHWCFG1 and GHWCFG2 registers values.
static uint32_t calc_num_out_eps (dwc_otg_core_if_t *core_if)
 This function calculates the number of OUT EPS using GHWCFG1 and GHWCFG2 registers values.
void dwc_otg_core_init (dwc_otg_core_if_t *core_if)
 This function initializes the DWC_otg controller registers and prepares the core for device mode or host mode operation.
void dwc_otg_enable_device_interrupts (dwc_otg_core_if_t *core_if)
 This function enables the Device mode interrupts.
void dwc_otg_core_dev_init (dwc_otg_core_if_t *core_if)
 This function initializes the DWC_otg controller registers for device mode.
void dwc_otg_enable_host_interrupts (dwc_otg_core_if_t *core_if)
 This function enables the Host mode interrupts.
void dwc_otg_disable_host_interrupts (dwc_otg_core_if_t *core_if)
 This function disables the Host Mode interrupts.
void dwc_otg_core_host_init (dwc_otg_core_if_t *core_if)
 This function initializes the DWC_otg controller registers for host mode.
void dwc_otg_hc_init (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
 Prepares a host channel for transferring packets to/from a specific endpoint.
void dwc_otg_hc_halt (dwc_otg_core_if_t *core_if, dwc_hc_t *hc, dwc_otg_halt_status_e halt_status)
 Attempts to halt a host channel.
void dwc_otg_hc_cleanup (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
 Clears the transfer state for a host channel.
static void hc_set_even_odd_frame (dwc_otg_core_if_t *core_if, dwc_hc_t *hc, hcchar_data_t *hcchar)
 Sets the channel property that indicates in which frame a periodic transfer should occur.
void set_pid_isoc (dwc_hc_t *hc)
void dwc_otg_hc_start_transfer (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
 This function does the setup for a data transfer for a host channel and starts the transfer.
void dwc_otg_hc_start_transfer_ddma (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
 This function does the setup for a data transfer for a host channel and starts the transfer in Descriptor DMA mode.
int dwc_otg_hc_continue_transfer (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
 This function continues a data transfer that was started by previous call to dwc_otg_hc_start_transfer.
void dwc_otg_hc_do_ping (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
 Starts a PING transfer.
void dwc_otg_hc_write_packet (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
uint32_t dwc_otg_get_frame_number (dwc_otg_core_if_t *core_if)
 Gets the current USB frame number.
void dwc_otg_read_setup_packet (dwc_otg_core_if_t *core_if, uint32_t *dest)
 This function reads a setup packet from the Rx FIFO into the destination buffer.
void dwc_otg_ep0_activate (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function enables EP0 OUT to receive SETUP packets and configures EP0 IN for transmitting packets.
void dwc_otg_ep_activate (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function activates an EP.
void dwc_otg_ep_deactivate (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function deactivates an EP.
static void init_dma_desc_chain (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function initializes dma descriptor chain.
void dwc_otg_ep_start_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function does the setup for a data transfer for an EP and starts the transfer.
void dwc_otg_ep_start_zl_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function setup a zero length transfer in Buffer DMA and Slave modes for usb requests with zero field set.
void dwc_otg_ep0_start_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function does the setup for a data transfer for EP0 and starts the transfer.
void dwc_otg_ep0_continue_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function continues control IN transfers started by dwc_otg_ep0_start_transfer, when the transfer does not fit in a single packet.
static void dump_msg (const u8 *buf, unsigned int length)
void dwc_otg_ep_write_packet (dwc_otg_core_if_t *core_if, dwc_ep_t *ep, int dma)
 This function writes a packet into the Tx FIFO associated with the EP.
void dwc_otg_ep_set_stall (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 Set the EP STALL.
void dwc_otg_ep_clear_stall (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 Clear the EP STALL.
void dwc_otg_read_packet (dwc_otg_core_if_t *core_if, uint8_t *dest, uint16_t bytes)
 This function reads a packet from the Rx FIFO into the destination buffer.
void dwc_otg_dump_dev_registers (dwc_otg_core_if_t *core_if)
 Dump core registers and SPRAM.
void dwc_otg_dump_spram (dwc_otg_core_if_t *core_if)
 This functions reads the SPRAM and prints its content.
void dwc_otg_dump_host_registers (dwc_otg_core_if_t *core_if)
 This function reads the host registers and prints them.
void dwc_otg_dump_global_registers (dwc_otg_core_if_t *core_if)
 This function reads the core global registers and prints them.
void dwc_otg_flush_tx_fifo (dwc_otg_core_if_t *core_if, const int num)
 Flush a Tx FIFO.
void dwc_otg_flush_rx_fifo (dwc_otg_core_if_t *core_if)
 Flush Rx FIFO.
void dwc_otg_core_reset (dwc_otg_core_if_t *core_if)
 Do core a soft reset of the core.
uint8_t dwc_otg_is_device_mode (dwc_otg_core_if_t *_core_if)
uint8_t dwc_otg_is_host_mode (dwc_otg_core_if_t *_core_if)
void dwc_otg_cil_register_hcd_callbacks (dwc_otg_core_if_t *core_if, dwc_otg_cil_callbacks_t *cb, void *p)
 Register HCD callbacks.
void dwc_otg_cil_register_pcd_callbacks (dwc_otg_core_if_t *core_if, dwc_otg_cil_callbacks_t *cb, void *p)
 Register PCD callbacks.
void write_isoc_frame_data (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function writes isoc data per 1 (micro)frame into tx fifo.
void dwc_otg_iso_ep_start_frm_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function initializes a descriptor chain for Isochronous transfer.
static void dwc_otg_set_uninitialized (int32_t *p, int size)
static int dwc_otg_param_initialized (int32_t val)
uint8_t dwc_otg_is_dma_enable (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_otg_cap (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies the OTG capabilities.
int32_t dwc_otg_get_param_otg_cap (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_opt (dwc_otg_core_if_t *core_if, int32_t val)
int32_t dwc_otg_get_param_opt (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_dma_enable (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether to use slave or DMA mode for accessing the data FIFOs.
int32_t dwc_otg_get_param_dma_enable (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_dma_desc_enable (dwc_otg_core_if_t *core_if, int32_t val)
 When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data FIFOs in device mode.
int32_t dwc_otg_get_param_dma_desc_enable (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_host_support_fs_ls_low_power (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode.
int32_t dwc_otg_get_param_host_support_fs_ls_low_power (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_enable_dynamic_fifo (dwc_otg_core_if_t *core_if, int32_t val)
 0 - Use cC FIFO size parameters 1 - Allow dynamic FIFO sizing (default)
int32_t dwc_otg_get_param_enable_dynamic_fifo (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_data_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
 Total number of 4-byte words in the data FIFO memory.
int32_t dwc_otg_get_param_data_fifo_size (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_dev_rx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
 Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled.
int32_t dwc_otg_get_param_dev_rx_fifo_size (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_dev_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
 Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled.
int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_host_rx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
 Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled.
int32_t dwc_otg_get_param_host_rx_fifo_size (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_host_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
 Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core.
int32_t dwc_otg_get_param_host_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_host_perio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
 Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled.
int32_t dwc_otg_get_param_host_perio_tx_fifo_size (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_max_transfer_size (dwc_otg_core_if_t *core_if, int32_t val)
 The maximum transfer size supported in bytes.
int32_t dwc_otg_get_param_max_transfer_size (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_max_packet_count (dwc_otg_core_if_t *core_if, int32_t val)
 The maximum number of packets in a transfer.
int32_t dwc_otg_get_param_max_packet_count (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_host_channels (dwc_otg_core_if_t *core_if, int32_t val)
 The number of host channel registers to use.
int32_t dwc_otg_get_param_host_channels (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_dev_endpoints (dwc_otg_core_if_t *core_if, int32_t val)
 The number of endpoints in addition to EP0 available for device mode operations.
int32_t dwc_otg_get_param_dev_endpoints (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_phy_type (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies the type of PHY interface to use.
int32_t dwc_otg_get_param_phy_type (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_speed (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies the maximum speed of operation in host and device mode.
int32_t dwc_otg_get_param_speed (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_host_ls_low_power_phy_clk (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode.
int32_t dwc_otg_get_param_host_ls_low_power_phy_clk (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_phy_ulpi_ddr (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether the ULPI operates at double or single data rate.
int32_t dwc_otg_get_param_phy_ulpi_ddr (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_phy_ulpi_ext_vbus (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether to use the internal or external supply to drive the vbus with a ULPI phy.
int32_t dwc_otg_get_param_phy_ulpi_ext_vbus (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_phy_utmi_width (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies the UTMI+ Data Width.
int32_t dwc_otg_get_param_phy_utmi_width (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_ulpi_fs_ls (dwc_otg_core_if_t *core_if, int32_t val)
int32_t dwc_otg_get_param_ulpi_fs_ls (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_ts_dline (dwc_otg_core_if_t *core_if, int32_t val)
int32_t dwc_otg_get_param_ts_dline (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_i2c_enable (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether to use the I2Cinterface for full speed PHY.
int32_t dwc_otg_get_param_i2c_enable (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_dev_perio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val, int fifo_num)
 Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled.
int32_t dwc_otg_get_param_dev_perio_tx_fifo_size (dwc_otg_core_if_t *core_if, int fifo_num)
int dwc_otg_set_param_en_multiple_tx_fifo (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether dedicated transmit FIFOs are enabled for non periodic IN endpoints in device mode 0 - No 1 - Yes.
int32_t dwc_otg_get_param_en_multiple_tx_fifo (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_dev_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val, int fifo_num)
int32_t dwc_otg_get_param_dev_tx_fifo_size (dwc_otg_core_if_t *core_if, int fifo_num)
int dwc_otg_set_param_thr_ctl (dwc_otg_core_if_t *core_if, int32_t val)
 Thresholding enable flag- bit 0 - enable non-ISO Tx thresholding bit 1 - enable ISO Tx thresholding bit 2 - enable Rx thresholding.
int32_t dwc_otg_get_param_thr_ctl (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_lpm_enable (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether LPM (Link Power Management) support is enabled.
int32_t dwc_otg_get_param_lpm_enable (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_tx_thr_length (dwc_otg_core_if_t *core_if, int32_t val)
 Thresholding length for Tx FIFOs in 32 bit DWORDs.
int32_t dwc_otg_get_param_tx_thr_length (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_rx_thr_length (dwc_otg_core_if_t *core_if, int32_t val)
 Thresholding length for Rx FIFOs in 32 bit DWORDs.
int32_t dwc_otg_get_param_rx_thr_length (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_dma_burst_size (dwc_otg_core_if_t *core_if, int32_t val)
 The DMA Burst size (applicable only for External DMA Mode).
int32_t dwc_otg_get_param_dma_burst_size (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_pti_enable (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether PTI enhancement is enabled.
int32_t dwc_otg_get_param_pti_enable (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_mpi_enable (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether MPI enhancement is enabled.
int32_t dwc_otg_get_param_mpi_enable (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_ic_usb_cap (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether IC_USB capability is enabled.
int32_t dwc_otg_get_param_ic_usb_cap (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_ahb_thr_ratio (dwc_otg_core_if_t *core_if, int32_t val)
int32_t dwc_otg_get_param_ahb_thr_ratio (dwc_otg_core_if_t *core_if)
uint32_t dwc_otg_get_hnpstatus (dwc_otg_core_if_t *core_if)
 Get host negotiation status.
uint32_t dwc_otg_get_srpstatus (dwc_otg_core_if_t *core_if)
 Get srp status.
void dwc_otg_set_hnpreq (dwc_otg_core_if_t *core_if, uint32_t val)
 Set hnpreq bit in the GOTGCTL register.
uint32_t dwc_otg_get_gsnpsid (dwc_otg_core_if_t *core_if)
 Get Content of SNPSID register.
uint32_t dwc_otg_get_mode (dwc_otg_core_if_t *core_if)
 Get current mode.
uint32_t dwc_otg_get_hnpcapable (dwc_otg_core_if_t *core_if)
 Get value of hnpcapable field in the GUSBCFG register.
void dwc_otg_set_hnpcapable (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of hnpcapable field in the GUSBCFG register.
uint32_t dwc_otg_get_srpcapable (dwc_otg_core_if_t *core_if)
 Get value of srpcapable field in the GUSBCFG register.
void dwc_otg_set_srpcapable (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of srpcapable field in the GUSBCFG register.
uint32_t dwc_otg_get_devspeed (dwc_otg_core_if_t *core_if)
 Get value of devspeed field in the DCFG register.
void dwc_otg_set_devspeed (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of devspeed field in the DCFG register.
uint32_t dwc_otg_get_busconnected (dwc_otg_core_if_t *core_if)
 Get the value of busconnected field from the HPRT0 register.
uint32_t dwc_otg_get_enumspeed (dwc_otg_core_if_t *core_if)
 Gets the device enumeration Speed.
uint32_t dwc_otg_get_prtpower (dwc_otg_core_if_t *core_if)
 Get value of prtpwr field from the HPRT0 register.
void dwc_otg_set_prtpower (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of prtpwr field from the HPRT0 register.
uint32_t dwc_otg_get_prtsuspend (dwc_otg_core_if_t *core_if)
 Get value of prtsusp field from the HPRT0 regsiter.
void dwc_otg_set_prtsuspend (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of prtpwr field from the HPRT0 register.
void dwc_otg_set_prtresume (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of prtres field from the HPRT0 register FIXME Remove?
uint32_t dwc_otg_get_remotewakesig (dwc_otg_core_if_t *core_if)
 Get value of rmtwkupsig bit in DCTL register.
uint32_t dwc_otg_get_lpm_portsleepstatus (dwc_otg_core_if_t *core_if)
 Get value of prt_sleep_sts field from the GLPMCFG register.
uint32_t dwc_otg_get_lpm_remotewakeenabled (dwc_otg_core_if_t *core_if)
 Get value of rem_wkup_en field from the GLPMCFG register.
uint32_t dwc_otg_get_lpmresponse (dwc_otg_core_if_t *core_if)
 Get value of appl_resp field from the GLPMCFG register.
void dwc_otg_set_lpmresponse (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of appl_resp field from the GLPMCFG register.
uint32_t dwc_otg_get_hsic_connect (dwc_otg_core_if_t *core_if)
 Get value of hsic_connect field from the GLPMCFG register.
void dwc_otg_set_hsic_connect (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of hsic_connect field from the GLPMCFG register.
uint32_t dwc_otg_get_inv_sel_hsic (dwc_otg_core_if_t *core_if)
 Get value of inv_sel_hsic field from the GLPMCFG register.
void dwc_otg_set_inv_sel_hsic (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of inv_sel_hsic field from the GLPMFG register.
uint32_t dwc_otg_get_gotgctl (dwc_otg_core_if_t *core_if)
 GOTGCTL register.
void dwc_otg_set_gotgctl (dwc_otg_core_if_t *core_if, uint32_t val)
uint32_t dwc_otg_get_gusbcfg (dwc_otg_core_if_t *core_if)
 GUSBCFG register.
void dwc_otg_set_gusbcfg (dwc_otg_core_if_t *core_if, uint32_t val)
uint32_t dwc_otg_get_grxfsiz (dwc_otg_core_if_t *core_if)
 GRXFSIZ register.
void dwc_otg_set_grxfsiz (dwc_otg_core_if_t *core_if, uint32_t val)
uint32_t dwc_otg_get_gnptxfsiz (dwc_otg_core_if_t *core_if)
 GNPTXFSIZ register.
void dwc_otg_set_gnptxfsiz (dwc_otg_core_if_t *core_if, uint32_t val)
uint32_t dwc_otg_get_gpvndctl (dwc_otg_core_if_t *core_if)
void dwc_otg_set_gpvndctl (dwc_otg_core_if_t *core_if, uint32_t val)
uint32_t dwc_otg_get_ggpio (dwc_otg_core_if_t *core_if)
 GGPIO register.
void dwc_otg_set_ggpio (dwc_otg_core_if_t *core_if, uint32_t val)
uint32_t dwc_otg_get_hprt0 (dwc_otg_core_if_t *core_if)
 HPRT0 register.
void dwc_otg_set_hprt0 (dwc_otg_core_if_t *core_if, uint32_t val)
uint32_t dwc_otg_get_guid (dwc_otg_core_if_t *core_if)
 GUID register.
void dwc_otg_set_guid (dwc_otg_core_if_t *core_if, uint32_t val)
uint32_t dwc_otg_get_hptxfsiz (dwc_otg_core_if_t *core_if)
 GHPTXFSIZE.

Detailed Description

The Core Interface Layer provides basic services for accessing and managing the DWC_otg hardware.

These services are used by both the Host Controller Driver and the Peripheral Controller Driver.

The CIL manages the memory map for the core so that the HCD and PCD don't have to do this separately. It also handles basic tasks like reading/writing the registers and data FIFOs in the controller. Some of the data access functions provide encapsulation of several operations required to perform a task, such as writing multiple registers to start a transfer. Finally, the CIL performs basic services that are not specific to either the host or device modes of operation. These services include management of the OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). A Diagnostic API is also provided to allow testing of the controller hardware.

The Core Interface Layer has the following requirements:

Definition in file dwc_otg_cil.c.

Define Documentation

#define DWC_OTG_PARAM_TEST ( _param_,
_low_,
_high_   ) 

Value:

(((_param_) < (_low_)) || \
                ((_param_) > (_high_)))

Definition at line 4051 of file dwc_otg_cil.c.

Function Documentation

dwc_otg_core_if_t* dwc_otg_cil_init ( const uint32_t *  reg_base_addr  ) 

This function is called to initialize the DWC_otg CSR data structures.

The register addresses in the device and host structures are initialized from the base address supplied by the caller. The calling function must make the OS calls to get the base address of the DWC_otg controller registers. The core_params argument holds the parameters that specify how the core should be configured.

Parameters:
reg_base_addr Base address of DWC_otg core registers

Definition at line 78 of file dwc_otg_cil.c.

void dwc_otg_cil_remove ( dwc_otg_core_if_t *  core_if  ) 

This function frees the structures allocated by dwc_otg_cil_init().

Parameters:
core_if The core interface pointer returned from dwc_otg_cil_init().

Definition at line 265 of file dwc_otg_cil.c.

void dwc_otg_enable_global_interrupts ( dwc_otg_core_if_t *  core_if  ) 

This function enables the controller's Global Interrupt in the AHB Config register.

Parameters:
core_if Programming view of DWC_otg controller.

Definition at line 292 of file dwc_otg_cil.c.

void dwc_otg_disable_global_interrupts ( dwc_otg_core_if_t *  core_if  ) 

This function disables the controller's Global Interrupt in the AHB Config register.

Parameters:
core_if Programming view of DWC_otg controller.

Definition at line 305 of file dwc_otg_cil.c.

static void dwc_otg_enable_common_interrupts ( dwc_otg_core_if_t *  core_if  )  [static]

This function initializes the commmon interrupts, used in both device and host modes.

Parameters:
core_if Programming view of the DWC_otg controller

Definition at line 319 of file dwc_otg_cil.c.

static uint32_t calc_num_in_eps ( dwc_otg_core_if_t *  core_if  )  [static]

This function calculates the number of IN EPS using GHWCFG1 and GHWCFG2 registers values.

Parameters:
core_if Programming view of the DWC_otg controller

Definition at line 415 of file dwc_otg_cil.c.

static uint32_t calc_num_out_eps ( dwc_otg_core_if_t *  core_if  )  [static]

This function calculates the number of OUT EPS using GHWCFG1 and GHWCFG2 registers values.

Parameters:
core_if Programming view of the DWC_otg controller

Definition at line 444 of file dwc_otg_cil.c.

void dwc_otg_core_init ( dwc_otg_core_if_t *  core_if  ) 

This function initializes the DWC_otg controller registers and prepares the core for device mode or host mode operation.

Parameters:
core_if Programming view of the DWC_otg controller

Definition at line 467 of file dwc_otg_cil.c.

void dwc_otg_enable_device_interrupts ( dwc_otg_core_if_t *  core_if  ) 

This function enables the Device mode interrupts.

Parameters:
core_if Programming view of DWC_otg controller

Todo:
NGS: Should this be a module parameter?

Definition at line 772 of file dwc_otg_cil.c.

void dwc_otg_core_dev_init ( dwc_otg_core_if_t *  core_if  ) 

This function initializes the DWC_otg controller registers for device mode.

Parameters:
core_if Programming view of DWC_otg controller

Set Periodic Tx FIFO Mask all bits 0

Set Tx FIFO Mask all bits 0

Todo:
NGS: Fix Periodic FIFO Sizing!

Todo:
Finish debug of this

Todo:
  • if the condition needed to be checked or in any case all pending interrutps should be cleared?

Definition at line 843 of file dwc_otg_cil.c.

void dwc_otg_enable_host_interrupts ( dwc_otg_core_if_t *  core_if  ) 

This function enables the Host mode interrupts.

Parameters:
core_if Programming view of DWC_otg controller

Definition at line 1130 of file dwc_otg_cil.c.

void dwc_otg_disable_host_interrupts ( dwc_otg_core_if_t *  core_if  ) 

This function disables the Host Mode interrupts.

Parameters:
core_if Programming view of DWC_otg controller

Definition at line 1165 of file dwc_otg_cil.c.

void dwc_otg_core_host_init ( dwc_otg_core_if_t *  core_if  ) 

This function initializes the DWC_otg controller registers for host mode.

This function flushes the Tx and Rx FIFOs and it flushes any entries in the request queues. Host channels are reset to ensure that they are ready for performing transfers.

Parameters:
core_if Programming view of DWC_otg controller

Definition at line 1196 of file dwc_otg_cil.c.

void dwc_otg_hc_init ( dwc_otg_core_if_t *  core_if,
dwc_hc_t *  hc 
)

Prepares a host channel for transferring packets to/from a specific endpoint.

The HCCHARn register is set up with the characteristics specified in _hc. Host channel interrupts that may need to be serviced while this transfer is in progress are enabled.

Parameters:
core_if Programming view of DWC_otg controller
hc Information needed to initialize the host channel

Definition at line 1352 of file dwc_otg_cil.c.

void dwc_otg_hc_halt ( dwc_otg_core_if_t *  core_if,
dwc_hc_t *  hc,
dwc_otg_halt_status_e  halt_status 
)

Attempts to halt a host channel.

This function should only be called in Slave mode or to abort a transfer in either Slave mode or DMA mode. Under normal circumstances in DMA mode, the controller halts the channel when the transfer is complete or a condition occurs that requires application intervention.

In slave mode, checks for a free request queue entry, then sets the Channel Enable and Channel Disable bits of the Host Channel Characteristics register of the specified channel to intiate the halt. If there is no free request queue entry, sets only the Channel Disable bit of the HCCHARn register to flush requests for this channel. In the latter case, sets a flag to indicate that the host channel needs to be halted when a request queue slot is open.

In DMA mode, always sets the Channel Enable and Channel Disable bits of the HCCHARn register. The controller ensures there is space in the request queue before submitting the halt request.

Some time may elapse before the core flushes any posted requests for this host channel and halts. The Channel Halted interrupt handler completes the deactivation of the host channel.

Parameters:
core_if Controller register interface.
hc Host channel to halt.
halt_status Reason for halting the channel.

Definition at line 1540 of file dwc_otg_cil.c.

void dwc_otg_hc_cleanup ( dwc_otg_core_if_t *  core_if,
dwc_hc_t *  hc 
)

Clears the transfer state for a host channel.

This function is normally called after a transfer is done and the host channel is being released.

Parameters:
core_if Programming view of DWC_otg controller.
hc Identifies the host channel to clean up.

Definition at line 1667 of file dwc_otg_cil.c.

static void hc_set_even_odd_frame ( dwc_otg_core_if_t *  core_if,
dwc_hc_t *  hc,
hcchar_data_t *  hcchar 
) [inline, static]

Sets the channel property that indicates in which frame a periodic transfer should occur.

This is always set to the _next_ frame. This function has no effect on non-periodic transfers.

Parameters:
core_if Programming view of DWC_otg controller.
hc Identifies the host channel to set up and its properties.
hcchar Current value of the HCCHAR register for the specified host channel.

Definition at line 1695 of file dwc_otg_cil.c.

void dwc_otg_hc_start_transfer ( dwc_otg_core_if_t *  core_if,
dwc_hc_t *  hc 
)

This function does the setup for a data transfer for a host channel and starts the transfer.

May be called in either Slave mode or DMA mode. In Slave mode, the caller must ensure that there is sufficient space in the request queue and Tx Data FIFO.

For an OUT transfer in Slave mode, it loads a data packet into the appropriate FIFO. If necessary, additional data packets will be loaded in the Host ISR.

For an IN transfer in Slave mode, a data packet is requested. The data packets are unloaded from the Rx FIFO in the Host ISR. If necessary, additional data packets are requested in the Host ISR.

For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ register along with a packet count of 1 and the channel is enabled. This causes a single PING transaction to occur. Other fields in HCTSIZ are simply set to 0 since no data transfer occurs in this case.

For a PING transfer in DMA mode, the HCTSIZ register is initialized with all the information required to perform the subsequent data transfer. In addition, the Do Ping bit is set in the HCTSIZ register. In this case, the controller performs the entire PING protocol, then starts the data transfer.

Parameters:
core_if Programming view of DWC_otg controller.
hc Information needed to initialize the host channel. The xfer_len value may be reduced to accommodate the max widths of the XferSize and PktCnt fields in the HCTSIZn register. The multi_count value may be changed to reflect the final xfer_len value.

Definition at line 1800 of file dwc_otg_cil.c.

void dwc_otg_hc_start_transfer_ddma ( dwc_otg_core_if_t *  core_if,
dwc_hc_t *  hc 
)

This function does the setup for a data transfer for a host channel and starts the transfer in Descriptor DMA mode.

Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set. Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field with micro-frame bitmap.

Initializes HCDMA register with descriptor list address and CTD value then starts the transfer via enabling the channel.

Parameters:
core_if Programming view of DWC_otg controller.
hc Information needed to initialize the host channel.

Definition at line 1968 of file dwc_otg_cil.c.

int dwc_otg_hc_continue_transfer ( dwc_otg_core_if_t *  core_if,
dwc_hc_t *  hc 
)

This function continues a data transfer that was started by previous call to dwc_otg_hc_start_transfer.

The caller must ensure there is sufficient space in the request queue and Tx Data FIFO. This function should only be called in Slave mode. In DMA mode, the controller acts autonomously to complete transfers programmed to a host channel.

For an OUT transfer, a new data packet is loaded into the appropriate FIFO if there is any data remaining to be queued. For an IN transfer, another data packet is always requested. For the SETUP phase of a control transfer, this function does nothing.

Returns:
1 if a new request is queued, 0 if no more requests are required for this transfer.

Definition at line 2048 of file dwc_otg_cil.c.

void dwc_otg_hc_do_ping ( dwc_otg_core_if_t *  core_if,
dwc_hc_t *  hc 
)

Starts a PING transfer.

This function should only be called in Slave mode. The Do Ping bit is set in the HCTSIZ register, then the channel is enabled.

Definition at line 2110 of file dwc_otg_cil.c.

uint32_t dwc_otg_get_frame_number ( dwc_otg_core_if_t *  core_if  ) 

Gets the current USB frame number.

This is the frame number from the last SOF packet.

Definition at line 2182 of file dwc_otg_cil.c.

void dwc_otg_read_setup_packet ( dwc_otg_core_if_t *  core_if,
uint32_t *  dest 
)

This function reads a setup packet from the Rx FIFO into the destination buffer.

This function is called from the Rx Status Queue Level (RxStsQLvl) Interrupt routine when a SETUP packet has been received in Slave mode.

Parameters:
core_if Programming view of DWC_otg controller.
dest Destination buffer for packet data.

Definition at line 2199 of file dwc_otg_cil.c.

void dwc_otg_ep0_activate ( dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)

This function enables EP0 OUT to receive SETUP packets and configures EP0 IN for transmitting packets.

It is normally called when the "Enumeration Done" interrupt occurs.

Parameters:
core_if Programming view of DWC_otg controller.
ep The EP0 data.

Definition at line 2216 of file dwc_otg_cil.c.

void dwc_otg_ep_activate ( dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)

This function activates an EP.

The Device EP control register for the EP is configured as defined in the ep structure. Note: This function is not used for EP0.

Parameters:
core_if Programming view of DWC_otg controller.
ep The EP to activate.

Definition at line 2268 of file dwc_otg_cil.c.

void dwc_otg_ep_deactivate ( dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)

This function deactivates an EP.

This is done by clearing the USB Active EP bit in the Device EP control register. Note: This function is not used for EP0. EP0 cannot be deactivated.

Parameters:
core_if Programming view of DWC_otg controller.
ep The EP to deactivate.

Definition at line 2367 of file dwc_otg_cil.c.

static void init_dma_desc_chain ( dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
) [static]

This function initializes dma descriptor chain.

Parameters:
core_if Programming view of DWC_otg controller.
ep The EP to start the transfer on.

DMA Descriptor Setup

Definition at line 2415 of file dwc_otg_cil.c.

void dwc_otg_ep_start_transfer ( dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)

This function does the setup for a data transfer for an EP and starts the transfer.

For an IN transfer, the packets will be loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are unloaded from the Rx FIFO in the ISR. the ISR.

Parameters:
core_if Programming view of DWC_otg controller.
ep The EP to start the transfer on.

DIEPDMAn Register write

Enable the Non-Periodic Tx FIFO empty interrupt, or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, the data will be written into the fifo by the ISR.

DOEPDMAn Register write

Definition at line 2475 of file dwc_otg_cil.c.

void dwc_otg_ep_start_zl_transfer ( dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)

This function setup a zero length transfer in Buffer DMA and Slave modes for usb requests with zero field set.

Parameters:
core_if Programming view of DWC_otg controller.
ep The EP to start the transfer on.

Enable the Non-Periodic Tx FIFO empty interrupt, or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, the data will be written into the fifo by the ISR.

Definition at line 2678 of file dwc_otg_cil.c.

void dwc_otg_ep0_start_transfer ( dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)

This function does the setup for a data transfer for EP0 and starts the transfer.

For an IN transfer, the packets will be loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are unloaded from the Rx FIFO in the ISR.

Parameters:
core_if Programming view of DWC_otg controller.
ep The EP0 data.

DMA Descriptor Setup

DIEPDMA0 Register write

Enable the Non-Periodic Tx FIFO empty interrupt, the data will be written into the fifo by the ISR.

DMA Descriptor Setup

DOEPDMA0 Register write

Definition at line 2785 of file dwc_otg_cil.c.

void dwc_otg_ep0_continue_transfer ( dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)

This function continues control IN transfers started by dwc_otg_ep0_start_transfer, when the transfer does not fit in a single packet.

NOTE: The DIEPCTL0/DOEPCTL0 registers only have one bit for the packet count.

Parameters:
core_if Programming view of DWC_otg controller.
ep The EP0 data.

Todo:
Should there be check for room in the Tx Status Queue. If not remove the code above this comment.

DMA Descriptor Setup

DIEPDMA0 Register write

Enable the Non-Periodic Tx FIFO empty interrupt, the data will be written into the fifo by the ISR.

DMA Descriptor Setup

DOEPDMA0 Register write

Definition at line 2969 of file dwc_otg_cil.c.

void dwc_otg_ep_write_packet ( dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep,
int  dma 
)

This function writes a packet into the Tx FIFO associated with the EP.

For non-periodic EPs the non-periodic Tx FIFO is written. For periodic EPs the periodic Tx FIFO associated with the EP is written with all packets for the next micro-frame.

Parameters:
core_if Programming view of DWC_otg controller.
ep The EP to write packet for.
dma Indicates if DMA is being used.

The buffer is padded to DWORD on a per packet basis in slave/dma mode if the MPS is not DWORD aligned. The last packet, if short, is also padded to a multiple of DWORD.

ep->xfer_buff always starts DWORD aligned in memory and is a multiple of DWORD in length

ep->xfer_len can be any number of bytes

ep->xfer_count is a multiple of ep->maxpacket until the last packet

FIFO access is DWORD

Todo:
NGS Where are the Periodic Tx FIFO addresses intialized? What should this be?

Definition at line 3165 of file dwc_otg_cil.c.

void dwc_otg_ep_set_stall ( dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)

Set the EP STALL.

Parameters:
core_if Programming view of DWC_otg controller.
ep The EP to set the stall on.

Definition at line 3236 of file dwc_otg_cil.c.

void dwc_otg_ep_clear_stall ( dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)

Clear the EP STALL.

Parameters:
core_if Programming view of DWC_otg controller.
ep The EP to clear stall from.

Definition at line 3274 of file dwc_otg_cil.c.

void dwc_otg_read_packet ( dwc_otg_core_if_t *  core_if,
uint8_t *  dest,
uint16_t  bytes 
)

This function reads a packet from the Rx FIFO into the destination buffer.

To read SETUP data use dwc_otg_read_setup_packet.

Parameters:
core_if Programming view of DWC_otg controller.
dest Destination buffer for the packet.
bytes Number of bytes to copy to the destination.

Todo:
Account for the case where _dest is not dword aligned. This requires reading data from the FIFO into a uint32_t temp buffer, then moving it into the data buffer.

Definition at line 3317 of file dwc_otg_cil.c.

void dwc_otg_dump_dev_registers ( dwc_otg_core_if_t *  core_if  ) 

Dump core registers and SPRAM.

Parameters:
core_if Programming view of DWC_otg controller.

Definition at line 3347 of file dwc_otg_cil.c.

void dwc_otg_dump_spram ( dwc_otg_core_if_t *  core_if  ) 

This functions reads the SPRAM and prints its content.

Parameters:
core_if Programming view of DWC_otg controller.

Definition at line 3477 of file dwc_otg_cil.c.

void dwc_otg_dump_host_registers ( dwc_otg_core_if_t *  core_if  ) 

This function reads the host registers and prints them.

Parameters:
core_if Programming view of DWC_otg controller.

Definition at line 3505 of file dwc_otg_cil.c.

void dwc_otg_dump_global_registers ( dwc_otg_core_if_t *  core_if  ) 

This function reads the core global registers and prints them.

Parameters:
core_if Programming view of DWC_otg controller.

Definition at line 3573 of file dwc_otg_cil.c.

void dwc_otg_flush_tx_fifo ( dwc_otg_core_if_t *  core_if,
const int  num 
)

Flush a Tx FIFO.

Parameters:
core_if Programming view of DWC_otg controller.
num Tx FIFO to flush.

Definition at line 3662 of file dwc_otg_cil.c.

void dwc_otg_flush_rx_fifo ( dwc_otg_core_if_t *  core_if  ) 

Flush Rx FIFO.

Parameters:
core_if Programming view of DWC_otg controller.

Definition at line 3694 of file dwc_otg_cil.c.

void dwc_otg_core_reset ( dwc_otg_core_if_t *  core_if  ) 

Do core a soft reset of the core.

Be careful with this because it resets all the internal state machines of the core.

Definition at line 3725 of file dwc_otg_cil.c.

void dwc_otg_cil_register_hcd_callbacks ( dwc_otg_core_if_t *  core_if,
dwc_otg_cil_callbacks_t *  cb,
void *  p 
)

Register HCD callbacks.

The callbacks are used to start and stop the HCD for interrupt processing.

Parameters:
core_if Programming view of DWC_otg controller.
cb the HCD callback structure.
p pointer to be passed to callback function (usb_hcd*).

Definition at line 3781 of file dwc_otg_cil.c.

void dwc_otg_cil_register_pcd_callbacks ( dwc_otg_core_if_t *  core_if,
dwc_otg_cil_callbacks_t *  cb,
void *  p 
)

Register PCD callbacks.

The callbacks are used to start and stop the PCD for interrupt processing.

Parameters:
core_if Programming view of DWC_otg controller.
cb the PCD callback structure.
p pointer to be passed to callback function (pcd*).

Definition at line 3796 of file dwc_otg_cil.c.

void write_isoc_frame_data ( dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)

This function writes isoc data per 1 (micro)frame into tx fifo.

Parameters:
core_if Programming view of DWC_otg controller.
ep The EP to start the transfer on.

Definition at line 3812 of file dwc_otg_cil.c.

void dwc_otg_iso_ep_start_frm_transfer ( dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)

This function initializes a descriptor chain for Isochronous transfer.

Parameters:
core_if Programming view of DWC_otg controller.
ep The EP to start the transfer on.

Enable endpoint, clear nak

Definition at line 3864 of file dwc_otg_cil.c.

int dwc_otg_set_param_otg_cap ( dwc_otg_core_if_t *  core_if,
int32_t  val 
)

Specifies the OTG capabilities.

The driver will automatically detect the value for this parameter if none is specified. 0 - HNP and SRP capable (default) 1 - SRP Only capable 2 - No HNP/SRP capable

Definition at line 4056 of file dwc_otg_cil.c.

int dwc_otg_set_param_dma_enable ( dwc_otg_core_if_t *  core_if,
int32_t  val 
)

Specifies whether to use slave or DMA mode for accessing the data FIFOs.

The driver will automatically detect the value for this parameter if none is specified. 0 - Slave 1 - DMA (default, if available)

Definition at line 4135 of file dwc_otg_cil.c.

int dwc_otg_set_param_dma_desc_enable ( dwc_otg_core_if_t *  core_if,
int32_t  val 
)

When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data FIFOs in device mode.

The driver will automatically detect the value for this parameter if none is specified. 0 - address DMA 1 - DMA Descriptor(default, if available)

Definition at line 4165 of file dwc_otg_cil.c.

int dwc_otg_set_param_host_support_fs_ls_low_power ( dwc_otg_core_if_t *  core_if,
int32_t  val 
)

Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode.

0 - Don't support low power mode (default) 1 - Support low power mode

Definition at line 4195 of file dwc_otg_cil.c.

int dwc_otg_set_param_data_fifo_size ( dwc_otg_core_if_t *  core_if,
int32_t  val 
)

Total number of 4-byte words in the data FIFO memory.

This memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs. 32 to 32768 (default 8192) Note: The total FIFO memory depth in the FPGA configuration is 8192.

Definition at line 4242 of file dwc_otg_cil.c.

int dwc_otg_set_param_dev_rx_fifo_size ( dwc_otg_core_if_t *  core_if,
int32_t  val 
)

Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled.

16 to 32768 (default 1064)

Definition at line 4271 of file dwc_otg_cil.c.

int dwc_otg_set_param_dev_nperio_tx_fifo_size ( dwc_otg_core_if_t *  core_if,
int32_t  val 
)

Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled.

16 to 32768 (default 1024)

Definition at line 4297 of file dwc_otg_cil.c.

int dwc_otg_set_param_host_rx_fifo_size ( dwc_otg_core_if_t *  core_if,
int32_t  val 
)

Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled.

16 to 32768 (default 1024)

Definition at line 4330 of file dwc_otg_cil.c.

int dwc_otg_set_param_host_nperio_tx_fifo_size ( dwc_otg_core_if_t *  core_if,
int32_t  val 
)

Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core.

16 to 32768 (default 1024)

Definition at line 4362 of file dwc_otg_cil.c.

int dwc_otg_set_param_host_perio_tx_fifo_size ( dwc_otg_core_if_t *  core_if,
int32_t  val 
)

Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled.

16 to 32768 (default 1024)

Definition at line 4395 of file dwc_otg_cil.c.

int dwc_otg_set_param_max_transfer_size ( dwc_otg_core_if_t *  core_if,
int32_t  val 
)

The maximum transfer size supported in bytes.

2047 to 65,535 (default 65,535)

Definition at line 4428 of file dwc_otg_cil.c.

int dwc_otg_set_param_max_packet_count ( dwc_otg_core_if_t *  core_if,
int32_t  val 
)

The maximum number of packets in a transfer.

15 to 511 (default 511)

Definition at line 4461 of file dwc_otg_cil.c.

int dwc_otg_set_param_host_channels ( dwc_otg_core_if_t *  core_if,
int32_t  val 
)

The number of host channel registers to use.

1 to 16 (default 12) Note: The FPGA configuration supports a maximum of 12 host channels.

Definition at line 4492 of file dwc_otg_cil.c.

int dwc_otg_set_param_dev_endpoints ( dwc_otg_core_if_t *  core_if,
int32_t  val 
)

The number of endpoints in addition to EP0 available for device mode operations.

1 to 15 (default 6 IN and OUT) Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in addition to EP0.

Definition at line 4522 of file dwc_otg_cil.c.

int dwc_otg_set_param_phy_type ( dwc_otg_core_if_t *  core_if,
int32_t  val 
)

Specifies the type of PHY interface to use.

By default, the driver will automatically detect the phy_type.

0 - Full Speed PHY 1 - UTMI+ (default) 2 - ULPI

Definition at line 4552 of file dwc_otg_cil.c.

int dwc_otg_set_param_speed ( dwc_otg_core_if_t *  core_if,
int32_t  val 
)

Specifies the maximum speed of operation in host and device mode.

The actual speed depends on the speed of the attached device and the value of phy_type. The actual speed depends on the speed of the attached device. 0 - High Speed (default) 1 - Full Speed

Definition at line 4601 of file dwc_otg_cil.c.

int dwc_otg_set_param_host_ls_low_power_phy_clk ( dwc_otg_core_if_t *  core_if,
int32_t  val 
)

Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode.

This parameter is applicable only if HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS then defaults to 6 MHZ otherwise 48 MHZ.

0 - 48 MHz 1 - 6 MHz

Definition at line 4630 of file dwc_otg_cil.c.

int dwc_otg_set_param_phy_ulpi_ddr ( dwc_otg_core_if_t *  core_if,
int32_t  val 
)

Specifies whether the ULPI operates at double or single data rate.

This parameter is only applicable if PHY_TYPE is ULPI.

0 - single data rate ULPI interface with 8 bit wide data bus (default) 1 - double data rate ULPI interface with 4 bit wide data bus

Definition at line 4665 of file dwc_otg_cil.c.

int dwc_otg_set_param_phy_utmi_width ( dwc_otg_core_if_t *  core_if,
int32_t  val 
)

Specifies the UTMI+ Data Width.

This parameter is applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI PHY_TYPE, this parameter indicates the data width between the MAC and the ULPI Wrapper.) Also, this parameter is applicable only if the OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the core has been configured to work at either data path width.

8 or 16 bits (default 16)

Definition at line 4700 of file dwc_otg_cil.c.

int dwc_otg_set_param_i2c_enable ( dwc_otg_core_if_t *  core_if,
int32_t  val 
)

Specifies whether to use the I2Cinterface for full speed PHY.

This parameter is only applicable if PHY_TYPE is FS. 0 - No (default) 1 - Yes

Definition at line 4751 of file dwc_otg_cil.c.

int dwc_otg_set_param_dev_perio_tx_fifo_size ( dwc_otg_core_if_t *  core_if,
int32_t  val,
int  fifo_num 
)

Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled.

4 to 768 (default 256)

Definition at line 4779 of file dwc_otg_cil.c.

int dwc_otg_set_param_dma_burst_size ( dwc_otg_core_if_t *  core_if,
int32_t  val 
)

The DMA Burst size (applicable only for External DMA Mode).

1, 4, 8 16, 32, 64, 128, 256 (default 32)

Definition at line 4959 of file dwc_otg_cil.c.

uint32_t dwc_otg_get_mode ( dwc_otg_core_if_t *  core_if  ) 

Get current mode.

Returns 0 if in device mode, and 1 if in host mode.

Definition at line 5115 of file dwc_otg_cil.c.

Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  doxygen 1.4.7