dwc_otg_core_if structure contains information needed to manage the DWC_otg controller acting in either host or device mode.
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#include <dwc_otg_cil.h>
Data Fields | |
| dwc_otg_core_params_t * | core_params |
| Parameters that define how the core should be configured. | |
| dwc_otg_core_global_regs_t * | core_global_regs |
| Core Global registers starting at offset 000h. | |
| dwc_otg_dev_if_t * | dev_if |
| Device-specific information. | |
| dwc_otg_host_if_t * | host_if |
| Host-specific information. | |
| uint32_t | snpsid |
| Value from SNPSID register. | |
| uint8_t | phy_init_done |
| uint8_t | srp_success |
| uint8_t | srp_timer_started |
| volatile uint32_t * | pcgcctl |
| Power and Clock Gating Control Register. | |
| uint32_t * | data_fifo [MAX_EPS_CHANNELS] |
| Push/pop addresses for endpoints or host channels. | |
| uint16_t | total_fifo_size |
| Total RAM for FIFOs (Bytes). | |
| uint16_t | rx_fifo_size |
| Size of Rx FIFO (Bytes). | |
| uint16_t | nperio_tx_fifo_size |
| Size of Non-periodic Tx FIFO (Bytes). | |
| uint8_t | dma_enable |
| 1 if DMA is enabled, 0 otherwise. | |
| uint8_t | dma_desc_enable |
| 1 if DMA descriptor is enabled, 0 otherwise. | |
| uint8_t | pti_enh_enable |
| 1 if PTI Enhancement mode is enabled, 0 otherwise. | |
| uint8_t | multiproc_int_enable |
| 1 if MPI Enhancement mode is enabled, 0 otherwise. | |
| uint8_t | en_multiple_tx_fifo |
| 1 if dedicated Tx FIFOs are enabled, 0 otherwise. | |
| uint8_t | queuing_high_bandwidth |
| Set to 1 if multiple packets of a high-bandwidth transfer is in process of being queued. | |
| hwcfg1_data_t | hwcfg1 |
| Hardware Configuration -- stored here for convenience. | |
| hwcfg2_data_t | hwcfg2 |
| hwcfg3_data_t | hwcfg3 |
| hwcfg4_data_t | hwcfg4 |
| hcfg_data_t | hcfg |
| Host and Device Configuration -- stored here for convenience. | |
| dcfg_data_t | dcfg |
| uint8_t | op_state |
| The operational State, during transations (a_host>>a_peripherial and b_device=>b_host) this may not match the core but allows the software to determine transitions. | |
| uint8_t | restart_hcd_on_session_req |
| Set to 1 if the HCD needs to be restarted on a session request interrupt. | |
| dwc_otg_cil_callbacks * | hcd_cb |
| HCD callbacks. | |
| dwc_otg_cil_callbacks * | pcd_cb |
| PCD callbacks. | |
| uint32_t | p_tx_msk |
| Device mode Periodic Tx FIFO Mask. | |
| uint32_t | tx_msk |
| Device mode Periodic Tx FIFO Mask. | |
| dwc_workq_t * | wq_otg |
| Workqueue object used for handling several interrupts. | |
| dwc_timer_t * | wkp_timer |
| Timer object used for handling "Wakeup Detected" Interrupt. | |
| dwc_otg_lx_state_e | lx_state |
| Lx state of device. | |
dwc_otg_core_if structure contains information needed to manage the DWC_otg controller acting in either host or device mode.
It represents the programming view of the controller as a whole.
Definition at line 680 of file dwc_otg_cil.h.
Set to 1 if the HCD needs to be restarted on a session request interrupt.
This is required if no connector ID status change has occurred since the HCD was last disconnected.
Definition at line 765 of file dwc_otg_cil.h.
1.4.7