dwc_otg_cil.h File Reference

This file contains the interface to the Core Interface Layer. More...

#include "dwc_os.h"
#include "dwc_list.h"
#include "dwc_otg_dbg.h"
#include "dwc_otg_regs.h"
#include "dwc_otg_core_if.h"

Go to the source code of this file.

Data Structures

struct  iso_pkt_info
 Information for each ISOC packet. More...
struct  dwc_ep
 The dwc_ep structure represents the state of a single endpoint when acting in device mode. More...
struct  dwc_hc
 Host channel descriptor. More...
struct  dwc_otg_core_params
 The following parameters may be specified when starting the module. More...
struct  dwc_otg_core_if
 The dwc_otg_core_if structure contains information needed to manage the DWC_otg controller acting in either host or device mode. More...
struct  dwc_otg_cil_callbacks
 DWC_otg CIL callback structure. More...

Host CIL Functions

The following functions support managing the DWC_otg controller in host mode.

#define clear_hc_int(_hc_regs_, _intr_)
#define disable_hc_int(_hc_regs_, _intr_)
void dwc_otg_hc_init (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
 Prepares a host channel for transferring packets to/from a specific endpoint.
void dwc_otg_hc_halt (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc, dwc_otg_halt_status_e _halt_status)
 Attempts to halt a host channel.
void dwc_otg_hc_cleanup (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
 Clears the transfer state for a host channel.
void dwc_otg_hc_start_transfer (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
 This function does the setup for a data transfer for a host channel and starts the transfer.
int dwc_otg_hc_continue_transfer (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
 This function continues a data transfer that was started by previous call to dwc_otg_hc_start_transfer.
void dwc_otg_hc_do_ping (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
 Starts a PING transfer.
void dwc_otg_hc_write_packet (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
void dwc_otg_enable_host_interrupts (dwc_otg_core_if_t *_core_if)
 This function enables the Host mode interrupts.
void dwc_otg_disable_host_interrupts (dwc_otg_core_if_t *_core_if)
 This function disables the Host Mode interrupts.
void dwc_otg_hc_start_transfer_ddma (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
 This function does the setup for a data transfer for a host channel and starts the transfer in Descriptor DMA mode.
static uint32_t dwc_otg_read_hprt0 (dwc_otg_core_if_t *_core_if)
 This function Reads HPRT0 in preparation to modify.

Device CIL Functions

The following functions support managing the DWC_otg controller in device mode.

void dwc_otg_wakeup (dwc_otg_core_if_t *_core_if)
void dwc_otg_read_setup_packet (dwc_otg_core_if_t *_core_if, uint32_t *_dest)
 This function reads a setup packet from the Rx FIFO into the destination buffer.
uint32_t dwc_otg_get_frame_number (dwc_otg_core_if_t *_core_if)
 Gets the current USB frame number.
void dwc_otg_ep0_activate (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
 This function enables EP0 OUT to receive SETUP packets and configures EP0 IN for transmitting packets.
void dwc_otg_ep_activate (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
 This function activates an EP.
void dwc_otg_ep_deactivate (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
 This function deactivates an EP.
void dwc_otg_ep_start_transfer (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
 This function does the setup for a data transfer for an EP and starts the transfer.
void dwc_otg_ep_start_zl_transfer (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
 This function setup a zero length transfer in Buffer DMA and Slave modes for usb requests with zero field set.
void dwc_otg_ep0_start_transfer (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
 This function does the setup for a data transfer for EP0 and starts the transfer.
void dwc_otg_ep0_continue_transfer (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
 This function continues control IN transfers started by dwc_otg_ep0_start_transfer, when the transfer does not fit in a single packet.
void dwc_otg_ep_write_packet (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep, int _dma)
 This function writes a packet into the Tx FIFO associated with the EP.
void dwc_otg_ep_set_stall (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
 Set the EP STALL.
void dwc_otg_ep_clear_stall (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
 Clear the EP STALL.
void dwc_otg_enable_device_interrupts (dwc_otg_core_if_t *_core_if)
 This function enables the Device mode interrupts.
void dwc_otg_iso_ep_start_frm_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function initializes a descriptor chain for Isochronous transfer.
void dwc_otg_iso_ep_start_buf_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function initializes a descriptor chain for Isochronous transfer.

Common CIL Functions

The following functions support managing the DWC_otg controller in either device or host mode.

void dwc_otg_read_packet (dwc_otg_core_if_t *core_if, uint8_t *dest, uint16_t bytes)
 This function reads a packet from the Rx FIFO into the destination buffer.
void dwc_otg_flush_tx_fifo (dwc_otg_core_if_t *_core_if, const int _num)
 Flush a Tx FIFO.
void dwc_otg_flush_rx_fifo (dwc_otg_core_if_t *_core_if)
 Flush Rx FIFO.
void dwc_otg_core_reset (dwc_otg_core_if_t *_core_if)
 Do core a soft reset of the core.
static uint32_t dwc_otg_read_core_intr (dwc_otg_core_if_t *core_if)
 This function returns the Core Interrupt register.
static uint32_t dwc_otg_read_otg_intr (dwc_otg_core_if_t *core_if)
 This function returns the OTG Interrupt register.
static uint32_t dwc_otg_read_dev_all_in_ep_intr (dwc_otg_core_if_t *core_if)
 This function reads the Device All Endpoints Interrupt register and returns the IN endpoint interrupt bits.
static uint32_t dwc_otg_read_dev_all_out_ep_intr (dwc_otg_core_if_t *core_if)
 This function reads the Device All Endpoints Interrupt register and returns the OUT endpoint interrupt bits.
static uint32_t dwc_otg_read_dev_in_ep_intr (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function returns the Device IN EP Interrupt register.
static uint32_t dwc_otg_read_dev_out_ep_intr (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
 This function returns the Device OUT EP Interrupt register.
static uint32_t dwc_otg_read_host_all_channels_intr (dwc_otg_core_if_t *_core_if)
 This function returns the Host All Channel Interrupt register.
static uint32_t dwc_otg_read_host_channel_intr (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
static uint32_t dwc_otg_mode (dwc_otg_core_if_t *_core_if)
 This function returns the mode of the operation, host or device.

Defines

#define __DWC_CIL_H__
#define OTG_CORE_REV_2_60a   0x4F54260A
 Macros defined for DWC OTG HW Release verison.
#define OTG_CORE_REV_2_71a   0x4F54271A
#define OTG_CORE_REV_2_72a   0x4F54272A
#define OTG_CORE_REV_2_80a   0x4F54280A
#define OTG_CORE_REV_2_81a   0x4F54281A
#define OTG_CORE_REV_2_90a   0x4F54290A
#define DWC_OTG_EP_TYPE_CONTROL   0
#define DWC_OTG_EP_TYPE_ISOC   1
#define DWC_OTG_EP_TYPE_BULK   2
#define DWC_OTG_EP_TYPE_INTR   3
#define DWC_OTG_EP_SPEED_LOW   0
#define DWC_OTG_EP_SPEED_FULL   1
#define DWC_OTG_EP_SPEED_HIGH   2
#define DWC_OTG_HC_PID_DATA0   0
#define DWC_OTG_HC_PID_DATA2   1
#define DWC_OTG_HC_PID_DATA1   2
#define DWC_OTG_HC_PID_MDATA   3
#define DWC_OTG_HC_PID_SETUP   3
#define DWC_OTG_PCGCCTL_OFFSET   0xE00
#define DWC_OTG_DATA_FIFO_OFFSET   0x1000
#define DWC_OTG_DATA_FIFO_SIZE   0x1000
#define A_HOST   (1)
 A-Device is a_host.
#define A_SUSPEND   (2)
 A-Device is a_suspend.
#define A_PERIPHERAL   (3)
 A-Device is a_peripherial.
#define B_PERIPHERAL   (4)
 B-Device is operating as a Peripheral.
#define B_HOST   (5)
 B-Device is operating as a Host.

Typedefs

typedef iso_pkt_info iso_pkt_info_t
 Information for each ISOC packet.
typedef dwc_ep dwc_ep_t
 The dwc_ep structure represents the state of a single endpoint when acting in device mode.
typedef enum dwc_otg_halt_status dwc_otg_halt_status_e
typedef dwc_hc dwc_hc_t
 Host channel descriptor.
typedef dwc_otg_core_params dwc_otg_core_params_t
 The following parameters may be specified when starting the module.
typedef enum dwc_otg_lx_state dwc_otg_lx_state_e
typedef dwc_otg_cil_callbacks dwc_otg_cil_callbacks_t
 DWC_otg CIL callback structure.

Enumerations

enum  dwc_otg_halt_status {
  DWC_OTG_HC_XFER_NO_HALT_STATUS, DWC_OTG_HC_XFER_COMPLETE, DWC_OTG_HC_XFER_URB_COMPLETE, DWC_OTG_HC_XFER_ACK,
  DWC_OTG_HC_XFER_NAK, DWC_OTG_HC_XFER_NYET, DWC_OTG_HC_XFER_STALL, DWC_OTG_HC_XFER_XACT_ERR,
  DWC_OTG_HC_XFER_FRAME_OVERRUN, DWC_OTG_HC_XFER_BABBLE_ERR, DWC_OTG_HC_XFER_DATA_TOGGLE_ERR, DWC_OTG_HC_XFER_AHB_ERR,
  DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE, DWC_OTG_HC_XFER_URB_DEQUEUE
}
enum  dwc_otg_lx_state { DWC_OTG_L0, DWC_OTG_L1, DWC_OTG_L2, DWC_OTG_L3 }

Functions

void w_conn_id_status_change (void *p)
void w_wakeup_detected (void *p)
void dwc_otg_core_host_init (dwc_otg_core_if_t *_core_if)
 This function initializes the DWC_otg controller registers for host mode.
void dwc_otg_core_dev_init (dwc_otg_core_if_t *_core_if)
 This function initializes the DWC_otg controller registers for device mode.
void dwc_otg_cil_register_pcd_callbacks (dwc_otg_core_if_t *_core_if, dwc_otg_cil_callbacks_t *_cb, void *_p)
 Register PCD callbacks.
void dwc_otg_cil_register_hcd_callbacks (dwc_otg_core_if_t *_core_if, dwc_otg_cil_callbacks_t *_cb, void *_p)
 Register HCD callbacks.

Detailed Description

This file contains the interface to the Core Interface Layer.

Definition in file dwc_otg_cil.h.

Define Documentation

#define clear_hc_int ( _hc_regs_,
_intr_   ) 

Value:

do { \
        hcint_data_t hcint_clear = {.d32 = 0}; \
        hcint_clear.b._intr_ = 1; \
        dwc_write_reg32(&(_hc_regs_)->hcint, hcint_clear.d32); \
} while (0)

Definition at line 903 of file dwc_otg_cil.h.

#define disable_hc_int ( _hc_regs_,
_intr_   ) 

Value:

do { \
        hcintmsk_data_t hcintmsk = {.d32 = 0}; \
        hcintmsk.b._intr_ = 1; \
        dwc_modify_reg32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \
} while (0)

Definition at line 917 of file dwc_otg_cil.h.

Typedef Documentation

typedef struct dwc_ep dwc_ep_t

The dwc_ep structure represents the state of a single endpoint when acting in device mode.

It contains the data items needed for an endpoint to be activated and transfer packets.

typedef struct dwc_hc dwc_hc_t

Host channel descriptor.

This structure represents the state of a single host channel when acting in host mode. It contains the data items needed to transfer packets to an endpoint via a host channel.

typedef struct dwc_otg_core_params dwc_otg_core_params_t

The following parameters may be specified when starting the module.

These parameters define how the DWC_otg controller should be configured.

typedef struct dwc_otg_cil_callbacks dwc_otg_cil_callbacks_t

DWC_otg CIL callback structure.

This structure allows the HCD and PCD to register functions used for starting and stopping the PCD and HCD for role change on for a DRD.

Enumeration Type Documentation

enum dwc_otg_lx_state

Enumerator:
DWC_OTG_L0  On state.
DWC_OTG_L1  LPM sleep state.
DWC_OTG_L2  USB suspend state.
DWC_OTG_L3  Off state.

Definition at line 664 of file dwc_otg_cil.h.

Function Documentation

void w_wakeup_detected ( void *  p  ) 

Definition at line 473 of file dwc_otg_cil_intr.c.

void dwc_otg_core_host_init ( dwc_otg_core_if_t *  core_if  ) 

This function initializes the DWC_otg controller registers for host mode.

This function flushes the Tx and Rx FIFOs and it flushes any entries in the request queues. Host channels are reset to ensure that they are ready for performing transfers.

Parameters:
core_if Programming view of DWC_otg controller

Definition at line 1196 of file dwc_otg_cil.c.

void dwc_otg_core_dev_init ( dwc_otg_core_if_t *  core_if  ) 

This function initializes the DWC_otg controller registers for device mode.

Parameters:
core_if Programming view of DWC_otg controller

Set Periodic Tx FIFO Mask all bits 0

Set Tx FIFO Mask all bits 0

Todo:
NGS: Fix Periodic FIFO Sizing!

Todo:
Finish debug of this

Todo:
  • if the condition needed to be checked or in any case all pending interrutps should be cleared?

Definition at line 843 of file dwc_otg_cil.c.

void dwc_otg_read_setup_packet ( dwc_otg_core_if_t *  core_if,
uint32_t *  dest 
)

This function reads a setup packet from the Rx FIFO into the destination buffer.

This function is called from the Rx Status Queue Level (RxStsQLvl) Interrupt routine when a SETUP packet has been received in Slave mode.

Parameters:
core_if Programming view of DWC_otg controller.
dest Destination buffer for packet data.

Definition at line 2199 of file dwc_otg_cil.c.

uint32_t dwc_otg_get_frame_number ( dwc_otg_core_if_t *  core_if  ) 

Gets the current USB frame number.

This is the frame number from the last SOF packet.

Definition at line 2182 of file dwc_otg_cil.c.

void dwc_otg_ep0_activate ( dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)

This function enables EP0 OUT to receive SETUP packets and configures EP0 IN for transmitting packets.

It is normally called when the "Enumeration Done" interrupt occurs.

Parameters:
core_if Programming view of DWC_otg controller.
ep The EP0 data.

Definition at line 2216 of file dwc_otg_cil.c.

void dwc_otg_ep_activate ( dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)

This function activates an EP.

The Device EP control register for the EP is configured as defined in the ep structure. Note: This function is not used for EP0.

Parameters:
core_if Programming view of DWC_otg controller.
ep The EP to activate.

Definition at line 2268 of file dwc_otg_cil.c.

void dwc_otg_ep_deactivate ( dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)

This function deactivates an EP.

This is done by clearing the USB Active EP bit in the Device EP control register. Note: This function is not used for EP0. EP0 cannot be deactivated.

Parameters:
core_if Programming view of DWC_otg controller.
ep The EP to deactivate.

Definition at line 2367 of file dwc_otg_cil.c.

void dwc_otg_ep_start_transfer ( dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)

This function does the setup for a data transfer for an EP and starts the transfer.

For an IN transfer, the packets will be loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are unloaded from the Rx FIFO in the ISR. the ISR.

Parameters:
core_if Programming view of DWC_otg controller.
ep The EP to start the transfer on.

DIEPDMAn Register write

Enable the Non-Periodic Tx FIFO empty interrupt, or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, the data will be written into the fifo by the ISR.

DOEPDMAn Register write

Definition at line 2475 of file dwc_otg_cil.c.

void dwc_otg_ep_start_zl_transfer ( dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)

This function setup a zero length transfer in Buffer DMA and Slave modes for usb requests with zero field set.

Parameters:
core_if Programming view of DWC_otg controller.
ep The EP to start the transfer on.

Enable the Non-Periodic Tx FIFO empty interrupt, or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, the data will be written into the fifo by the ISR.

Definition at line 2678 of file dwc_otg_cil.c.

void dwc_otg_ep0_start_transfer ( dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)

This function does the setup for a data transfer for EP0 and starts the transfer.

For an IN transfer, the packets will be loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are unloaded from the Rx FIFO in the ISR.

Parameters:
core_if Programming view of DWC_otg controller.
ep The EP0 data.

DMA Descriptor Setup

DIEPDMA0 Register write

Enable the Non-Periodic Tx FIFO empty interrupt, the data will be written into the fifo by the ISR.

DMA Descriptor Setup

DOEPDMA0 Register write

Definition at line 2785 of file dwc_otg_cil.c.

void dwc_otg_ep0_continue_transfer ( dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)

This function continues control IN transfers started by dwc_otg_ep0_start_transfer, when the transfer does not fit in a single packet.

NOTE: The DIEPCTL0/DOEPCTL0 registers only have one bit for the packet count.

Parameters:
core_if Programming view of DWC_otg controller.
ep The EP0 data.

Todo:
Should there be check for room in the Tx Status Queue. If not remove the code above this comment.

DMA Descriptor Setup

DIEPDMA0 Register write

Enable the Non-Periodic Tx FIFO empty interrupt, the data will be written into the fifo by the ISR.

DMA Descriptor Setup

DOEPDMA0 Register write

Definition at line 2969 of file dwc_otg_cil.c.

void dwc_otg_ep_write_packet ( dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep,
int  dma 
)

This function writes a packet into the Tx FIFO associated with the EP.

For non-periodic EPs the non-periodic Tx FIFO is written. For periodic EPs the periodic Tx FIFO associated with the EP is written with all packets for the next micro-frame.

Parameters:
core_if Programming view of DWC_otg controller.
ep The EP to write packet for.
dma Indicates if DMA is being used.

The buffer is padded to DWORD on a per packet basis in slave/dma mode if the MPS is not DWORD aligned. The last packet, if short, is also padded to a multiple of DWORD.

ep->xfer_buff always starts DWORD aligned in memory and is a multiple of DWORD in length

ep->xfer_len can be any number of bytes

ep->xfer_count is a multiple of ep->maxpacket until the last packet

FIFO access is DWORD

Todo:
NGS Where are the Periodic Tx FIFO addresses intialized? What should this be?

Definition at line 3165 of file dwc_otg_cil.c.

void dwc_otg_ep_set_stall ( dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)

Set the EP STALL.

Parameters:
core_if Programming view of DWC_otg controller.
ep The EP to set the stall on.

Definition at line 3236 of file dwc_otg_cil.c.

void dwc_otg_ep_clear_stall ( dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)

Clear the EP STALL.

Parameters:
core_if Programming view of DWC_otg controller.
ep The EP to clear stall from.

Definition at line 3274 of file dwc_otg_cil.c.

void dwc_otg_enable_device_interrupts ( dwc_otg_core_if_t *  core_if  ) 

This function enables the Device mode interrupts.

Parameters:
core_if Programming view of DWC_otg controller

Todo:
NGS: Should this be a module parameter?

Definition at line 772 of file dwc_otg_cil.c.

void dwc_otg_iso_ep_start_frm_transfer ( dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)

This function initializes a descriptor chain for Isochronous transfer.

Parameters:
core_if Programming view of DWC_otg controller.
ep The EP to start the transfer on.

Enable endpoint, clear nak

Definition at line 3864 of file dwc_otg_cil.c.

void dwc_otg_iso_ep_start_buf_transfer ( dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)

This function initializes a descriptor chain for Isochronous transfer.

Parameters:
core_if Programming view of DWC_otg controller.
ep The EP to start the transfer on.

Enable endpoint, clear nak

Definition at line 517 of file dwc_otg_pcd.c.

void dwc_otg_hc_init ( dwc_otg_core_if_t *  core_if,
dwc_hc_t *  hc 
)

Prepares a host channel for transferring packets to/from a specific endpoint.

The HCCHARn register is set up with the characteristics specified in _hc. Host channel interrupts that may need to be serviced while this transfer is in progress are enabled.

Parameters:
core_if Programming view of DWC_otg controller
hc Information needed to initialize the host channel

Definition at line 1352 of file dwc_otg_cil.c.

void dwc_otg_hc_halt ( dwc_otg_core_if_t *  core_if,
dwc_hc_t *  hc,
dwc_otg_halt_status_e  halt_status 
)

Attempts to halt a host channel.

This function should only be called in Slave mode or to abort a transfer in either Slave mode or DMA mode. Under normal circumstances in DMA mode, the controller halts the channel when the transfer is complete or a condition occurs that requires application intervention.

In slave mode, checks for a free request queue entry, then sets the Channel Enable and Channel Disable bits of the Host Channel Characteristics register of the specified channel to intiate the halt. If there is no free request queue entry, sets only the Channel Disable bit of the HCCHARn register to flush requests for this channel. In the latter case, sets a flag to indicate that the host channel needs to be halted when a request queue slot is open.

In DMA mode, always sets the Channel Enable and Channel Disable bits of the HCCHARn register. The controller ensures there is space in the request queue before submitting the halt request.

Some time may elapse before the core flushes any posted requests for this host channel and halts. The Channel Halted interrupt handler completes the deactivation of the host channel.

Parameters:
core_if Controller register interface.
hc Host channel to halt.
halt_status Reason for halting the channel.

Definition at line 1540 of file dwc_otg_cil.c.

void dwc_otg_hc_cleanup ( dwc_otg_core_if_t *  core_if,
dwc_hc_t *  hc 
)

Clears the transfer state for a host channel.

This function is normally called after a transfer is done and the host channel is being released.

Parameters:
core_if Programming view of DWC_otg controller.
hc Identifies the host channel to clean up.

Definition at line 1667 of file dwc_otg_cil.c.

void dwc_otg_hc_start_transfer ( dwc_otg_core_if_t *  core_if,
dwc_hc_t *  hc 
)

This function does the setup for a data transfer for a host channel and starts the transfer.

May be called in either Slave mode or DMA mode. In Slave mode, the caller must ensure that there is sufficient space in the request queue and Tx Data FIFO.

For an OUT transfer in Slave mode, it loads a data packet into the appropriate FIFO. If necessary, additional data packets will be loaded in the Host ISR.

For an IN transfer in Slave mode, a data packet is requested. The data packets are unloaded from the Rx FIFO in the Host ISR. If necessary, additional data packets are requested in the Host ISR.

For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ register along with a packet count of 1 and the channel is enabled. This causes a single PING transaction to occur. Other fields in HCTSIZ are simply set to 0 since no data transfer occurs in this case.

For a PING transfer in DMA mode, the HCTSIZ register is initialized with all the information required to perform the subsequent data transfer. In addition, the Do Ping bit is set in the HCTSIZ register. In this case, the controller performs the entire PING protocol, then starts the data transfer.

Parameters:
core_if Programming view of DWC_otg controller.
hc Information needed to initialize the host channel. The xfer_len value may be reduced to accommodate the max widths of the XferSize and PktCnt fields in the HCTSIZn register. The multi_count value may be changed to reflect the final xfer_len value.

Definition at line 1800 of file dwc_otg_cil.c.

int dwc_otg_hc_continue_transfer ( dwc_otg_core_if_t *  core_if,
dwc_hc_t *  hc 
)

This function continues a data transfer that was started by previous call to dwc_otg_hc_start_transfer.

The caller must ensure there is sufficient space in the request queue and Tx Data FIFO. This function should only be called in Slave mode. In DMA mode, the controller acts autonomously to complete transfers programmed to a host channel.

For an OUT transfer, a new data packet is loaded into the appropriate FIFO if there is any data remaining to be queued. For an IN transfer, another data packet is always requested. For the SETUP phase of a control transfer, this function does nothing.

Returns:
1 if a new request is queued, 0 if no more requests are required for this transfer.

Definition at line 2048 of file dwc_otg_cil.c.

void dwc_otg_hc_do_ping ( dwc_otg_core_if_t *  core_if,
dwc_hc_t *  hc 
)

Starts a PING transfer.

This function should only be called in Slave mode. The Do Ping bit is set in the HCTSIZ register, then the channel is enabled.

Definition at line 2110 of file dwc_otg_cil.c.

void dwc_otg_enable_host_interrupts ( dwc_otg_core_if_t *  core_if  ) 

This function enables the Host mode interrupts.

Parameters:
core_if Programming view of DWC_otg controller

Definition at line 1130 of file dwc_otg_cil.c.

void dwc_otg_disable_host_interrupts ( dwc_otg_core_if_t *  core_if  ) 

This function disables the Host Mode interrupts.

Parameters:
core_if Programming view of DWC_otg controller

Definition at line 1165 of file dwc_otg_cil.c.

void dwc_otg_hc_start_transfer_ddma ( dwc_otg_core_if_t *  core_if,
dwc_hc_t *  hc 
)

This function does the setup for a data transfer for a host channel and starts the transfer in Descriptor DMA mode.

Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set. Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field with micro-frame bitmap.

Initializes HCDMA register with descriptor list address and CTD value then starts the transfer via enabling the channel.

Parameters:
core_if Programming view of DWC_otg controller.
hc Information needed to initialize the host channel.

Definition at line 1968 of file dwc_otg_cil.c.

static uint32_t dwc_otg_read_hprt0 ( dwc_otg_core_if_t *  _core_if  )  [inline, static]

This function Reads HPRT0 in preparation to modify.

It keeps the WC bits 0 so that if they are read as 1, they won't clear when you write it back

Definition at line 929 of file dwc_otg_cil.h.

void dwc_otg_read_packet ( dwc_otg_core_if_t *  core_if,
uint8_t *  dest,
uint16_t  bytes 
)

This function reads a packet from the Rx FIFO into the destination buffer.

To read SETUP data use dwc_otg_read_setup_packet.

Parameters:
core_if Programming view of DWC_otg controller.
dest Destination buffer for the packet.
bytes Number of bytes to copy to the destination.

Todo:
Account for the case where _dest is not dword aligned. This requires reading data from the FIFO into a uint32_t temp buffer, then moving it into the data buffer.

Definition at line 3317 of file dwc_otg_cil.c.

void dwc_otg_flush_tx_fifo ( dwc_otg_core_if_t *  core_if,
const int  num 
)

Flush a Tx FIFO.

Parameters:
core_if Programming view of DWC_otg controller.
num Tx FIFO to flush.

Definition at line 3662 of file dwc_otg_cil.c.

void dwc_otg_flush_rx_fifo ( dwc_otg_core_if_t *  core_if  ) 

Flush Rx FIFO.

Parameters:
core_if Programming view of DWC_otg controller.

Definition at line 3694 of file dwc_otg_cil.c.

void dwc_otg_core_reset ( dwc_otg_core_if_t *  core_if  ) 

Do core a soft reset of the core.

Be careful with this because it resets all the internal state machines of the core.

Definition at line 3725 of file dwc_otg_cil.c.

static uint32_t dwc_otg_mode ( dwc_otg_core_if_t *  _core_if  )  [inline, static]

This function returns the mode of the operation, host or device.

Returns:
0 - Device Mode, 1 - Host Mode

Definition at line 1097 of file dwc_otg_cil.h.

void dwc_otg_cil_register_pcd_callbacks ( dwc_otg_core_if_t *  core_if,
dwc_otg_cil_callbacks_t *  cb,
void *  p 
)

Register PCD callbacks.

The callbacks are used to start and stop the PCD for interrupt processing.

Parameters:
core_if Programming view of DWC_otg controller.
cb the PCD callback structure.
p pointer to be passed to callback function (pcd*).

Definition at line 3796 of file dwc_otg_cil.c.

void dwc_otg_cil_register_hcd_callbacks ( dwc_otg_core_if_t *  core_if,
dwc_otg_cil_callbacks_t *  cb,
void *  p 
)

Register HCD callbacks.

The callbacks are used to start and stop the HCD for interrupt processing.

Parameters:
core_if Programming view of DWC_otg controller.
cb the HCD callback structure.
p pointer to be passed to callback function (usb_hcd*).

Definition at line 3781 of file dwc_otg_cil.c.

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