Résumé for Professor Simon Moore
Research and Industrial Experience
- July, 1998 onwards:
- University Lecturer, University of Cambridge, Computer Laboratory.
Promoted to Senior Lecturer in 2003 and Reader in Computer Architecture in 2008.
Professor of Computer Engineering from October 2014.
- October, 1998 onwards:
- Staff Fellow and Director of Studies, Trinity Hall, Cambridge.
- October, 1994 to June, 1998:
- Research Associate at the University of Cambridge. Initially funded
by EPSRC (grant GR/J 11140) and then by
ORL (which became AT&T Laboratories Cambridge) to investigate
self-timed circuit techniques.
- October, 1991 to September, 1994:
- Ph.D. by research at the University of Cambridge -
- 21st June to 10th September, 1993:
- Research intern at Digital Equipment Corporation, Western Research
Laboratory, 250 University Avenue, Palo Alto, California, CA94301.
- 26th July to 27th September, 1991:
- Research assistant to Professor J. W. Gardner at the
Department of Engineering, University of Warwick, Coventry,
CV4 7AL, England.
- During July 1986 to October 1990:
- Vacation employment (and undergraduate sponsorship) at Smiths
Industries - Aerospace Systems, Bishop's Cleeve, Cheltenham,
Gloucestershire, GL52 4SF, England.
Other Appointments and Affiliations
- IET Fellow (formally IEE) since 2011 and member since 1990. Served on the IET local committee including being chairman.
- IEEE member since September 1997, Senior Member since 2008
- Program Co-chair for the The Eighth IEEE International Symposium on Asynchronous Circuits and Systems, 2002
- EPSRC College member since 2003
- Frequent host of the UK Asynchronous Circuits Forum.
- Editorial Board of the Microprocessors and Microsystems Journal from 2003 to 2012
- Associate Editor for The Computer Journal since 2008
- Fellow of the BCS since 2009
Honours and Prizes
- Best paper award at the 2002 IEEE International Symposium on Asynchronous Circuits and Systems
- Elected a Fellow of the BCS in 2009
- Elected a Fellow of the IET in 2011
- Charted Engineer Status awarded in 2010
- Pilkington Teaching Prize winner in 2010 (also, news article)
- Ten year retrospective most influential paper prize at the Asia and South Pacific Design Automation Conference, 2016
External examining of PhD thesies
- Osama Albaharna, Area-Time Efficiency of FPGA-Based Computation, Department of Electrical Engineering, Imperial College London, 2003.
- An Yu, The Security of a VLSI Implementation of the New AES Against Power and Timing Attacks, Department of Computer Science, University of Manchester, 2003.
- Salvadore Sotelo-Salzar, Instruction Scheduling in Micronet-based Asynchronous ILP Processors, Department of Computer Science, University of Edinburgh, 2003.
- Andrew Royal, Globally Asynchronous Locally Synchronous Interconnect for Field Programmable Gate Arrays, Department of Electrical Engineering, Imperial College London, 2004.
- Vassilios Apostolos Chouliaras, Parallelism and the Software-Hardware Interface in Embedded Systems, Department of Electronic and Electrical Engineering, Loughborough University, 2005.
- Paul Capewell, Hardware Support for Embedded Java, Department of Computer Science, University of Manchester, 2006.
- Shi Zhong, A Micronet-based integrated soft- and hard- programmable multithreaded asynchronous architecture, Department of Computer Science, University of Edinburgh, 2006.
- Samuel Taylor, Data-Driven Handshake Circuit Synthesis, Department of Computer Science, University of Manchester, 2007.
- Julian Murphy, Standard cell and full custom power-balanced logic, School of Electrical, Electronic and Computer Engineering, Newcastle University, 2007.
- Andrew Robinson, Improving Instruction Encoding Efficiency in Low Power Microprocessors, Department of Computer Science, University of Manchester, 2009.
- Kieron Turkington, Datapath and memory co-optimization for FPGA-based computation, Department of Electrical Engineering, Imperial College London, 2009.
- Terrence Sui-Tung Mak, Circuit Design and Analysis for On-FPGA Communication Systems, Department of Electrical Engineering, Imperial College London, 2010.
- Shufan Yang, Memory Interconnect Management on a Chip Multiprocessor, Department of Computer Science, University of Manchester, 2010.
- Julain A. Bailey, Towards the Neurocomputer: an investigation of VHDL neuron models, Department of Electrical Engineering and Computer Science, University of Southampton, 2010.
- Philipp Grabher, Processor Design Techniques for Efficient and Secure Execution of Cryptographic Algorithms, University of Bristol, 2010.
- Markos Papadonikolakis, Mapping of Support Vector Machines on Field Programmable Gate Arrays, Imperial College London, 2012.
- Nehir Sonmez, A multicore emulator with a profiling infrastructure for transactional memory on FPGA, Universitat Politecnica de Catalunya, Barcelona, 2012.
- Adrien Le Masle, Reconfigurable Architectures for Cryptographic Systems, Department of Computer Science, Imperial College London, 2012.
- Matthias Boettcher, Memory and Functional Unit Design for Vector Microprocessors, Department of Electronics and Computer Science, University of Southampton, 2014.
- Xinyu Niu, Optimising runtime reconfigurable designs for high-performance applications, Imperial College London, 2015.
- David Lawson, Hierarchical Strategies for Fault-Tolerance in Reconfigurable Architectures, University of York, 2016.
- Oriol Arcas Abella, Multicore Architecture Prototyping on Reconfigurable Devices, Universitat Politècnica de Catalunya, Barcelona, 2016.
Chairman of Examiners (undergraduate examinations) in 2002 and 2015.PhD thesies:
- James Roy Bulpin, Operating Systems Support for Simultaneous Multithreaded Processors, 2004.
- Mbou Eyole-Monono, Energy Efficient Sentient Computing, 2008.
- Grzegorz Milos, Efficient and Effective Sharing of Memory in Virtual Machine Monitors, 2009.
- Saar Drimer, Security for volatile FPGAs, 2009.
- Daniel Bates, Exploiting tightly-coupled cores, 2013.
Graduated Ph.D. Students
I am always looking for bright Ph.D. students - see my Opportunities page.
I was the primary adviser for the following PhD students:
- Panit Watcharawitch, Multep: A Multithreaded Embedded Processor, 2003, now at FabriNet. [Technical Report]
- Simon Frankau, Hardware Synthesis from a stream-processing functional language, 2004 (jointly supervised with Alan Mycroft), now at Barclays Capital. [Technical Report]
- Scott Fairbanks, High Precision Timing Using Self-Timed Circuits, 2004, now at IBM Research. [Technical Report]
- Huiyun Li, Security Evaluation at Design Time for Cryptographic Hardware, 2005, now at the Chinese Academy of Sciences. [Technical Report]
- Jacques Fournier, Vector Microprocessors for Cryptography, 2007, now a research engineer at CAE-LETI. Previously a security architect at Gemalto. [Technical Report]
- Simon Hollis, Pulse-based, On-chip Interconnect, 2007, now a Lecturer at University of Bristol. [Technical Report]
- Ian Caulfield, Complexity-Effective Superscalar Embedded Processors Using Instruction-Level Distributed Processing, 2007, now an architect at ARM. [Technical Report]
- Matthew Johnson, A new approach to internet banking, 2008 [Technical Report]
- Alban Rrustemi, Computing surfaces - a platform for scalable ubiquitous interactive displays, 2008. Now working on a startup. [Technical Report]
- Arnab Banerjee, Communication Flows in Power-Efficient Networks-on-Chips, 2008. Imagination Technologies, UltraSoC, nVidia. [Technical Report]
- Philip Paul, Microelectronic security measures, 2009. Now at IBM Research in Zurich.. [Technical Report]
- Rosemary Francis, Exploring Networks-on-Chip for FPGAs, 2009. Setting up a company. [Technical Report]
- A. Theodore Markettos, Active Electromagnetic Attacks on Secure Hardware, 2010. Currently working as an RA with me. [Technical Report]
- Daniel Greenfield, Communication Locality in Computation: Software, Chip Multiprocessors and Brains, 2010. BCS Distinguished Dissertation Award Winner 2011.
- James Srinivasan, Improving cache utilisation, 2011. Now at 2d3. [Technical Report]
- Nick Barrow-Williams, Proximity Coherence for Chip-Multiprocessors, 2011. Now at nVidia in Santa Clara, CA, USA. [Technical Report]
- Meredydd Luff, Communication for Programmability and Performance on Multi-Core Processors, 2012. [Technical Report]
- Gregory Chadwick, Communication Centric Multi-Core, Fine Grained Processor Architecture, 2012. Now at Broadcom in Cambridge. [Technical Report]
- Paul Fox, Massively Parallel Neural Computation, 2013. Now an RA working with me. [Technical Report]
- Jonathan Woodruff, A RISC Capability System for Practical Memory Safety, 2014. Now an RA working with me. [Technical Report]
- Steven Marsh, Efficient programming models for neurocomputation, 2014.
- Robert Norton, Hardware support for compartmentalisation, 2015.
- Alan Mujumdar, Time-based memory coherence, submitted early 2016.
Before I started as a lecturer I co-supervised the following students with Prof. Peter Robinson:
- Steev Wilcox, Synthesis of asynchronous circuits, 1999. Previously Chief Architect and Director at Azuro (UK) Ltd, and now at Cadence. [Technical Report]
- Paul Cunningham, Verification of asynchronous circuit, 2002. Previously CEO at Azuro, Inc. and now Director of Research at Cadence. [Technical Report]
- For undergraduate teaching, please see my teaching page.
- I undertake director of studies duties for Trinity Hall (and have directed studies for Wolfson College, Peterhouse and New Hall). This encompasses the selection of prospective students, through monitoring and advising upon their studies, to writing references once they have left.
- Since October, 1991, I have performed supervision duties over a wide range of applied computer science subjects for a plethora of Cambridge colleges. I have also guided students to produce innovative projects in a range of subjects including processor design, self-timed circuit techniques, distributed simulation and visual concurrent programming, numerical analysis and many projects involving a hardware and software simulation and design.
Many of these papers are copyright of the respective journal or conference organizing body. These online copies are provided for your personal research use only.
You might find the Google Scholar information handy.
Yury Audzevich, Philip M. Watts, Andrew West, Alan Mujumdar, Simon W. Moore and Andrew W. Moore, Power Optimized Transceivers for Future Switched Networks, IEEE Transactions on VLSI Design, Vol. 22 Issue 10, pp. 2081-2092, September, 2013
Philip M. Watts, Simon W. Moore, and Andrew W. Moore, Energy Implications of Photonic Networks With Speculative Transmission, Journal of Optical Communications and Networking, Vol. 4 Issue 6, pp.503-513, 2012 (highlighted article)
Chris Fensch, Nick Barrow-Williams, Robert Mullins and Simon Moore, Designing a Physical Locality Aware Coherence Protocol for Chip-Multiprocessors, IEEE Transactions on Computers, Volume 62, Number 5, pp. 914-928, February 2012, (DOI: 10.1109/TC.2012.52)
Danielle S. Bassett, Daniel L. Greenfield, Andreas Meyer-Lindenberg, Daniel R. Weinberger, Simon W. Moore, Edward T. Bullmore, Efficient physical embedding of topologically complex information processing networks in brains and computer circuits, PLoS Computational Biology Journal, Volume 6, Issue 4, pp 1-14, April 2010. Journal Download (DOI: 10.1371/journal.pcbi.1000748)
Daniel Greenfield and Simon Moore, Implications of Electronics Technology Trends to Algorithm Design, The Computer Journal, Volume 52, Issue 6, pp 690-698, (DOI: 10.1093/comjnl/bxp013), April 2009. PDF version
Arnab Banerjee, Pascal Wolkotte, Robert Mullins, Simon Moore and Gerard Smit, An Energy and Performance Exploration of Network-on-Chip Architectures, In The IEEE Transactions on VLSI Systems Special Section on Networks-On-Chip, Vol 17 pp 319-329, 2009.
P. Oikonomakos, P. Paul, S.W. Moore, S. Tam, H. Ebihara, A dynamic-logic PLA on low-temperature polysilicon TFT technology, Electronic Letters number, Volume 43, Issue 5, pp 271-273, 1 March 2007. PDF version
Huiyun Li and Simon Moore, Security evaluation at design time against optical fault injection attacks, IEE Proceedings of Information Security, volume 153, number 1, pages 3-11, 2006.
J. Fournier and S. W. Moore, La carte à puce et les circuits asynchrones, numéro spécial de la 'Revue de l'Electricité et de l'Electronique des Technologies de l'Information et de la Communication', Août 2004.
Simon Moore, Ross Anderson, Robert Mullins, George Taylor, Jacques Fournier, Balanced Self-Checking Asynchronous Logic for Smart Card Applications, Microprocessors and Microsystems Journal, 27(9), pp 421-430, October 2003. PDF version
S. W. Moore, P Robinson and S. P. Wilcox, Rotary Pipeline Processors, IEE Part--E, Computers and Digital Techniques, Special Issue on Asynchronous Architectures, 143(5), pp 259--265, September 1996. PDF version
S.W. Moore, P.C. Paul and S. Tam, Smart-card chip with organic semiconductor surface layer for detecting invasive attack, UK Patent number GB2452763A, 14th September 2007. PDF USA Patent number US 8511567 B2 granted August 2013
S.W. Moore, P.C. Paul and S. Tam, Smart-card chip with organic conductive surface layer for detecting invasive attack, UK Patent number GB2452732A, 12th September 2007. PDF
S.W. Moore and M. Islam, Improvements in or Relating to Capacitance Sensors, British Patent Application Number: GB0203283.7, Initial filing 12 Feb 2002. USA patent version: Capacitance sensors with asynchronous ring oscillator circuit and capacitance, US Patent App. 10/503,227, 2003.
R.J. Anderson and S.W. Moore, Microprocessor Resistant to Power Analysis, International application number: PCT/GB01/00311, International filing date 26 January, 2001.
Refereed Conference Papers
Matthew Naylor and Simon W. Moore, A generic synthesisable test bench, 13th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE), 21-23 September 2015, Austin, TX, USA, pp 128-137.
Robert N. M. Watson, Jonathan Woodruff, Peter G. Neumann, Simon W. Moore, Jonathan Anderson, David Chisnall, Nirav Dave, Brooks Davis, Khilan Gudka, Ben Laurie, Steven J. Murdoch, Robert Norton, Michael Roe, Stacey Son, Munraj Vadera, CHERI: A Hybrid Capability-System Architecture for Scalable Software Compartmentalization, IEEE Symposium on Security and Privacy (aka Oakland), May 2015. (PDF)
David Chisnall, Colin Rothwell, Brooks Davis, Robert N.M. Watson, Jonathan Woodruff, Munraj Vadera, Simon W. Moore, Peter G. Neumann and Michael Roe. Beyond the PDP-11: Processor support for a memory-safe C abstract machine. Proceedings of the Fifteenth Edition of ASPLOS on Architectural Support for Programming Languages and Operating Systems, ACM, 2015. (PDF) Won the audience picks: best presentation award (well done to David Chisnall who presented our paper)
Matthew Naylor and Simon W. Moore, Rapid codesign of a soft vector processor and its compiler, 24th International Conference on Field Programmable Logic and Applications (FPL2014), 2-4 September 2014. (PDF)
Paul J. Fox, A. Theodore Markettos, Simon W. Moore and Andrew W. Moore, Interconnect for commodity FPGA clusters: standardized or customized?, 24th International Conference on Field Programmable Logic and Applications (FPL2014), 2-4 September 2014. (PDF)
Paul J. Fox, A. Theodore Markettos and Simon W. Moore, Reliably Prototyping Large SoCs Using FPGA Clusters, 9th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC'2014), 26-28 May 2014.
Jonathan Woodruff, Robert N. M. Watson, David Chisnall, Simon W. Moore, Jonathan Anderson, Brooks Davis, Ben Laurie, Peter G. Neumann, Robert Norton, and Michael Roe. The CHERI capability model: Revisiting RISC in an age of risk, Proceedings of the 41st International Symposium on Computer Architecture (ISCA 2014), 14–16 June, 2014, Minneapolis, MN, USA. (PDF)
Matthew Naylor, Paul J Fox, A Theodore Markettos and Simon W Moore, Managing the FPGA Memory Wall: custom computing or vector processing?, 23rd International Conference on Field Programmable Logic and Applications (FPL2013), September 2013. (PDF)
Gregory Chadwick and Simon Moore, Mamba - A Scalable Communication Centric Multithreaded Processor Architecture, IEEE International Conference on Computer Design (ICCD), pages 277-283, September 2012. (DOI: 10.1109/ICCD.2012.6378652)
Simon W. Moore, Paul J. Fox, Steven J.T. Marsh, A. Theo Markettos, Alan Mujumdar, Bluehive - A Field-Programmable Custom Computing Machine for Extreme-Scale Real-Time Neural Network Simulation, IEEE 20th International Symposium of Field-Programmable Custom Computing Machines (FCCM), pages 133-140, April 2012 (PDF preprint) (DOI: 10.1109/FCCM.2012.32).
Philip Watts, Nick Barrow-Williams and Simon Moore, Requirements of Low Power Photonic Networks for Distributed Shared Memory Computers, In proceedings of the Optical Fiber Communication Conference and Expositions (OFC) and the National Fiber Optic Engineers Conference (NFOEC), 2011.
Nick Barrow-Williams, Chris Fensch and Simon Moore, Proximity Coherence for Chip Multiprocessors, In proceedings of International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2010. (DOI: 10.1145/1854273.1854293)
A. T. Markettos and S. W. Moore, The Frequency Injection Attack on Ring-Oscillator-Based True Random Number Generators. In proceedings of Cryptographic Hardware and Embedded Systems (CHES), September 2009. LNCS 5747, pp 317-331.
Nick Barrow-Williams, Chris Fensch and Simon Moore, A Communication Characterisation of Splash-2 and Parsec, In Proceedings of the IEEE International Symposium on Workload Characterization, October 2009. PDF version
Arnab Banerjee and Simon Moore, Flow-aware allocation for on-chip networks, In Proceedings of the ACM/IEEE International Symposium on Networks-on-Chip, pages 183-192, 2009
Daniel Greenfield and Simon Moore, Implications of Electronics Technology Trends to Algorithm Design, In Proceedings of the BCS International Academic Conference on Visions of Computer Science, pages 331-342, 22-24 September 2008.
Philip Paul, Simon Moore and Simon Tam, Tamper Protection for Security Devices, ECSIS Symposium on Bio-inspired Learning and Intelligent Systems for Security, pages 92-96, August 2008.
Rosemary Francis, Simon Moore and Robert Mullins, A Network of Time-Division Multiplexed Wiring for FPGAs, In Proceedings of the 2nd ACM/IEEE Intl. Symp. on Networks-on-Chips, April 2008. (DOI: 10.1109/NOCS.2008.4492723)
Daniel Greenfield and Simon Moore, Fractal communication in software data dependency graphs, Proceedings of the ACM twentieth annual symposium on parallelism in algorithms and architectures, pages 116-118, June 2008.
Simon Moore and Daniel Greenfield, The Next Resource War: Computation vs. Communication, In the 10th International Workshop on System-Level Interconnect Prediction, April 2008.
Matthew Johnson and Simon Moore, A New Approach to E-Banking, Proc. 12th Nordic Workshop on Secure IT Systems (NORDSEC 2007), Oct 2007.
Arnab Banerjee, Robert Mullins and Simon Moore, A Power and Energy Exploration of Network-on-Chip Architectures, In Proceedings of the First Intl. Symp. on Networks-on-Chips, May 2007.
Daniel Greenfield, Arnab Banerjee, Jeong-Gun Lee and Simon Moore, Implications of Rent's rule for NoC design and its fault-tolerance, In Proceedings of the First Intl. Symp. on Networks-on-Chips, May 2007.
Kate Taylor and Simon Moore, Adding question answering to an e-tutor for programming languages, Applications and Innovations in Intelligent Systems XIV, Published by Springer London, pages 193-206, 2007.
Robert Mullins and Simon Moore, Demystifying Data-Driven and Pausible Clocking Schemes, In Proceedings of 13th IEEE Intl. Symp. on Asynchronous Circuits and Systems (ASYNC), March, 2007.
P. Oikonomakos and S.W. Moore, An Asynchronous PLA with Improved Security Characteristics, 9th Euromicro Conference on Digital System Design, Architectures, Methods and Tools (DSD06), Cavtat, Croatia 2006, pp 257-264. PDF version
S. Hollis and S.W. Moore, RasP: An area-efficient, on-chip network, In Proc. 24th International Conference on Computer Design (ICCD), Oct 2006.
J.J. Fournier and S.W. Moore, Hardware-software codesign of a vector co-processor for public key cryptography, 9th Euromicro Conference on Digital Systems Design, Croatia, August 2006
S. Hollis and S.W. Moore, An area-efficient, pulse-based interconnect, International Symposium on Circuits and Systems (ISCAS), May 2006.
P. Oikonomakos, J.J. Fournier and S.W. Moore, Implementing Cryptography on TFT Technology for Secure Display Applications, in the LNCS Proceedings of the 7th Smart Card Research and Advanced Application IFIP Conference (CARDIS'06), LNCS 3928 pp. 32-47, April 2006. PDF version
R.D. Mullins, A. West, S.W. Moore, The design and implementation of a low-latency on-chip network, 11th Asia and South Pacific Design Automation Conference (ASP-DAC), Japan, January 2006 PDF version - Won 10-year retrospective most influential paper prize
S. Hollis and S.W. Moore, An Asynchronous Interconnect Architecture for Device Security Enhancement, 19th International Conference on VLSI Design, January 2006. PDF version
J.J. Fournier and S.W. Moore, A vector approach to Cryptography Implementation, in the LNCS Proceedings of the 1st International Conference on Digital Rights Management Technologies Issues Challenges and Systems (DRMtics 2005), November 2005.
G.F. Roberts, R.V. Penty, I.H. White, A. West, S.W. Moore, Multi-wavelength data encoding for improved input power dynamic range in semiconductor optical amplifier switches, The 18th Annual Meeting of the IEEE Lasers and Electro-optics society (LEOS), Sydney, Australia, October 2005.
H. Li, A. A. T. Markettos and S. W. Moore, A Security Evaluation Methodology for Smart Cards Against Electromagnetic Analysis, in proceedings of 39th IEEE International Carnahan Conference on Security Technology (ICCST 2005), October 2005 PDF version
H. Li, A. A. T. Markettos and S. W. Moore, Security Evaluation Against Electromagnetic Analysis at Design Time, Workshop on Cryptographic Hardware and Embedded Systems (CHES), published by Springer in LNCS 3659, September 2005. PDF version
S. Fairbanks and S.W. Moore, Self-timed Circuitry for Global Clocking, 11th International Symposium on Asynchronous Circuits, March 2005 PDF version
R.D. Mullins, A. West, S.W. Moore, Low-Latency Virtual-Channel Routers for On-Chip Networks, ISCA, June 2004, PDF version
S. Fairbanks and S.W. Moore, High Precision Timing Signals Using Asynchronous Control Rings, 10th International Symposium on Asynchronous Circuits, April 2004 PDF version
J. Fournier, H. Li, S.W. Moore, R.D. Mullins, G.S. Taylor, Security Evaluation of Asynchronous Circuits, Workshop on Cryptographic Hardware and Embedded Systems (CHES), published by Springer in LNCS 2779, September 2003 PDF version
P. Watcharawitch and S.W. Moore, MulTEP: Multithreaded Embedded Processors, International Symposium on Low-Power and High-Speed Chips, Volume I, pp 355-361, April 2003.
P. Watcharawitch and S.W. Moore, JMA: The Java-Multithreading Architecture for Embedded Systems, International Conference on Computer Design, pp 527--530, September 2002. PDF version
Simon Moore, Ross Anderson, Paul Cunningham, Robert Mullins, George Taylor, Improving Smart Card Security using Self-timed Circuits, Eighth International Symposium on Advanced Research in Asynchronous Circuits and Systems, April 2002. PDF version
Simon Moore, George Taylor, Robert Mullins, Peter Robinson, Point-to-Point GALS Interconnect, Eighth International Symposium on Advanced Research in Asynchronous Circuits and Systems, 2002 PDF version
S.W. Moore, Protecting Consumer Security Devices --- The Next 10 Years, published by Springer in LNCS 2140, Cannes, September 2001.
S.W. Moore, G.S. Taylor, P.A. Cunningham, R.D. Mullins and P.Robinson, Self Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems, International Conference on Computer Design, Austin Texas, September 2000.
G.S. Taylor, S.W. Moore, P. Robinson, An on-chip dynamically recalibrated delay line for embedded self-timed systems, Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems, April 2000.
S. W. Moore and P. Robinson, Rapid Prototyping of Self-Timed Circuits, International Conference on Computer Design, Austin Texas, pp 360--365, October 1998.
S. W. Moore, Scalable temporally predictable memory structures, IEEE Real-time Applications Workshop, March 1994.
J. W. Gardner, W. Gopel, E. L. Hines, S. W. Moore and U. Weimar, A modified multilayer perceptron model for gas mixture analysis, Eurosensors VI, San Sebastian, Spain, September 1992.
S. W. Moore and G. Morgan, The recursive MOVE machine: r-move, IEE colloquium on RISC architectures and applications, November 1991.
Conference Posters/Abstracts/Breif Announcements
R. M. Francis and S. W. Moore, Exploring Hard and Soft Networks-on-Chip for FPGAs, In Proceedings of the IEEE International Conference on Field-Programmable Technology, Taiwan, December 2008.
Daniel Greenfield and Simon Moore, Brief Announcement: Fractal Communication in Software Data Dependency Graphs, In Proceedings of the 20th Annual ACM Symp. on Parallel Algorithms and Architectures, June 2008.
Meredydd Luff and Simon Moore, Asynchronous Remote Stores for Inter-Processor Communication, Future Architectural Support for Parallel Programming FASPP'12, June 2012. PDF
Robert N.M. Watson, Peter G. Neumann Jonathan Woodruff, Jonathan Anderson, Ross Anderson, Nirav Dave, Ben Laurie, Simon W. Moore, Steven J. Murdoch, Philip Paeps, Michael Roe, and Hassen Saidi, CHERI: a research platform deconflating hardware virtualization and protection, Workshop on Runtime Environments, Systems, Layering and Virtualized Environments (RESoLVE 2012), March, 2012. PDF
K. Taylor and S.W. Moore, My compiler really understand me: an adaptive programming language tutor, Adaptive Hypermedia and Adaptive Web-Based Systems, Springer, pages 389-392, 2006.
S. W. Moore and K. Taylor, An Intelligent Interactive Online Tutor for Computer Languages, 25th Annual International Conference of the British Computer Society's Specialist Group on Artificial Intelligence (SGAI), November 2005
R. D. Mullins, J.G. Lee and S.W. Moore, Selecting a Timing Regime for On-Chip Networks 17th UK Async. Forum, September 2005.
H. Li, A.T. Markettos, S.W. Moore, Security Evaluation Against Electromagnetic Analysis at Design Time IEEE International High Level Design Validation and Test Workshop 2005, Napa Valley, California, USA, December 2005.
Simon Hollis and Simon W. Moore, A Method of Thwarting EM Probe Attacks on IC Interconnect, PREP, March 2005. PDF version
A.T. Markettos and S.W. Moore, Electromagnetic Analysis of Synchronous and Asynchronous Circuits using Hard Disc Heads, 16th UK Async. Forum, September 2004. PDF version
H. Li, S.W. Moore and A.T.Markettos, A Simulation Methodology for Electromagnetic Analysis and Testing on Synchronous and Asynchronous Processors, 16th UK Async. Forum, September 2004. PDF version
P. Oikonomakos and S.W. Moore, Security Investigations on an Asynchronous PLA Configuration, 16th UK Async. Forum, September 2004. PDF version
S. Fairbanks and S.W. Moore, Asynchronous or synchronous: a misleading choice?, Fourth ACiD-WG Workshop (5th Framework Programme), Turku, Finland, June 2004. PDF version
S. Fairbanks and S.W. Moore, High precision timing signals with asynchronous control, 15th UK Async. Forum, January 2004.
H. Li and S.W. Moore, ROM Design and evaluation against power analysis attack, 15th UK Async. Forum, January 2004. PDF version
Huiyun Li, Simon Moore, Robert Mullins and George Taylor, Circuit Level Defences against Optical Fault Induction Attacks, 13th UK Async. Forum, December, 2002.
Simon Frankau, Alan Mycroft, Simon Moore, Statically-allocated languages for hardware stream processing, UK ACM SIGDA Workshop on Electronic Design Automation, 2002.
S.W. Moore, R. Mullins and G. Taylor, The Springbank Test Chip, 12th UK Async. Forum, June, 2002.
R.D. Mullins, S.W. Moore, G.S. Taylor, Designing one-of-four encoded datapaths, 12th UK Async. Forum, June, 2002.
George Taylor, Robert Mullins and Simon Moore, Exploiting both periodicity and asynchrony, Second ACiD-WG Workshop (5th Framework Programme), Munich, January 2002
Scott Fairbanks and Simon Moore, The Distributed Clock Generator, Second ACiD-WG Workshop (5th Framework Programme), Munich, January 2002
S.W.Moore, G.S.Taylor, R.D.Mullins and P.Robinson, Bundled-Data vs Clocked ASIC Design, 10th UK Async. Forum, July, 2001.
S.W.Moore, G.S.Taylor, R.D.Mullins and P.Robinson, Channel Communication Between Independent Clock Domains, Fifth ACiD-WG Workshop, Nauchatel, 2001.
P.A.Cunningham, P.Robinson, S.W.Moore, Veraci: A Verifier for Asynchronous Circuits, 9th UK Async. Forum, December, 2000.
S.W. Moore, G.S. Taylor, P.A. Cunningham, R.D. Mullins and P.Robinson, Using Stoppable Clocks to Safely Interface Asynchronous and Synchronous Subsystems, AINT (Asynchronous INTerfaces), Delft, Netherlands, July 2000. PDF version
S.W. Moore, G.S. Taylor, P.A. Cunningham, R.D. Mullins and P.Robinson, Clock Stretching Circuits, 8th UK Async. Forum, June, 2000.
S W Moore, R J Anderson, M G Kuhn, Improving Smartcard Security using Self-timed Circuit Technology, Fourth ACiD-WG Workshop, Grenoble, ISBN 2-913329-44-6, February 2000.
G S Taylor, S W Moore, P Robinson, Frequency Locked Loops: Adding Some Asynchronous Circuits to Synchronous Circuits, 7th UK Async. Forum, December 1999
P Cunningham, G S Taylor, P Robinson, S W Moore, Cheating Safely in Asynchronous Design, 7th UK Async. Forum, December1999
S P Wilcox, G S Taylor, S W Moore, P Robinson, Designing a 16-bit ALU for an Embedded Processor, 6th UK Async. Forum, July 1999
S W Moore, P Robinson, Geometry Planning for Self-Timed ASIC Design, ACiD-WG Workshop, Turin, January 1998.
S P Wilcox, S W Moore, P Robinson, Flow Table Synthesis, ACiD-WG Workshop, Turin, January 1998.
S W Moore, P Robinson, S Wilcox, RED Flip-Flops and Hybrid Completion Detection, ACiD-WG Workshop, University of Groningen technical report CSN 9602, September 1996.
S. W. Moore, Multithreaded Processor Design, Technical Report Number 358, Computer Laboratory, University of Cambridge, February, 1995.
The next resource war: computation vs. communication, IEEE/ACM Symposium on System Level Interconnect Prediction, 2008. Presented with Daniel Greenfield
Communication Centric Computer Design, Microelectronics and Embedded Systems event in Singapore. Invited by the British High Commission in Singapore (all expenses paid), January 2007.
Electronic Consumer Security Devices, Royal Academy of Engineering, Fellows' Technical Briefing on Engineering Out Crime, 8 May 2003
Clock tolerant architectures - asynchronous methods and issues, Workshop on Microprocessor Design, IEEE International Solid State Circuits Conference, San Francisco, 7 Feb 2002
Keynote talk at eSmart, Protecting Consumer Security Devices --- The Next 10 Years, published by Springer in LNCS 2140, Cannes, September 2001.
L. Lavagno and S. W. Moore, Breaking the synchronous barrier for Systems-on-Chip communication and synchronization, Design Automation Test Europe (DATE), March 2004
S W Moore, The benefits and pitfalls of using asynchronous circuits to build consumer security devices, 15th UK Async. Forum, January 2004.