Anaconda - A Multithreaded Processor
This work was published as a book
KLUWER ACADEMIC PUBLISHERS
Kluwer international series in engeering and computer science; SECS 0358.
ISBN: 0-7923-9718-5 Library of Congress Call Number: QA76.5 .M574 1996 Library of Congress Card Number: 96013326
The general purpose parallel computer is an elusive goal. Multithreaded processors have emerged as a promising solution to this conundrum by forming some amalgam of the common place control-flow (von Neumann) processor model and with the more exotic data-flow approach. This new processor model offers many exciting possibilities and there is much research to be performed to make this technology widespread.
This monograph takes the radical approach of designing a multithreaded processor from the ground up. Every aspect is carefully considered to form a balanced design rather than making incremental changes to an existing design and then ignoring problem areas.
Chapter 1 introduces the subject and Chapter 2 reviews the key hardware and software motivations which steer processor design in general. Best effort, hard real-time and multimedia application areas are assessed to determine desirable processor characteristics. Hardware limits are also addressed; in particular the need for efficient movement and synchronisation of data when using large memories and distributed processors.
Current control-flow and data-flow computer models are discussed in Chapter 3. Then the current state of the art in multithreaded processor design is reviewed in Chapter 4. This includes comparisons over a diverse range of designs from Tera to the Transputer and from Monsoon to *T.
Chapter 5 begins a more in depth look at the mechanisms required for multithreaded processor design, beginning with processor scheduling. A novel hardware scheduler, which can support earliest-deadline-first and fixed-priority scheduling schemes, is developed and implementation issues are discussed.
Chapter 6 discusses memory design and proposes a high bandwidth structure based upon a scalable space division interconnect. Suitable virtual address translation and protection mechanisms are also presented.
Chapter 7 draws on the scheduling and memory structure designs presented in Chapters 5 and 6. These are combined with a synchronisation mechanism and a control-flow processing core to support microthreaded multithreading, where a microthread is a short control-flow routine which is initiated in a data-flow manner.
Software issues are presented in Chapter 8 together with benchmarks used to evaluate the design. Finally, conclusions are drawn in Chapter 9.
Many friends and colleges at the University of Cambridge, Computer Laboratory have encouraged this work. Inparticular Brian Graham, Eoin Hyden and Derek McAuley have proved invaluable. I would also like to thank Alan Jones, Peter Robinson and David Wheeler for may thought-provoking discussions during the hardware discussion group meetings.
For reading and commenting on earlier versions of this work, I am indebted to Richard Black, Paul Byrne, Shaw Chuang, David Evers, Robin Fairbairns, Daniel Gordon and Johanna Stiebert.
Thanks are also due to Mike Hinchey for encouraging this version of the work and to Brett Saunders, Mary Ulicsak and Steve Wilcox for commenting on drafts.