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ACS P35-13/14 SoC D/M Vacation Slide Pack (RTL)

  • Vacation Pack
  • RTL: Register Transfer Language
  • RTL Summary View of Variant Forms.
  • Structural Verilog
  • Structure Flattening
  • 2a/3: Continuous Assignment.
  • 2b/3: Pure RTL : unordered synchronous register transfers.
  • 3/3: Behavioural RTL
  • Elementary Examples
  • Simulation And Synthesis.
  • SystemC: Hardware Modelling Library
  • Example (Counter)
  • SystemC Structural Netlist
  • SystemC Channels and Signals
  • SystemC: Abstracted Signals
  • SystemC Abstracted Data Modelling
  • Threads and Methods
  • Example using an SC_THREAD
  • Blocking and Eventing
  • Verilog RTL: Modules, Protocols and Interfaces
  • Protocol and Interface
  • Transactional Handshaking
  • Transactional Handshaking in RTL (Synchronous Example)
  • Hazards
  • Example: Sequential Long Multiplication
  • Multiplier Answer
  • Hazards From Array Memories
  • Overcoming Structural Hazards using Holding Registers
  • Folding, Retiming & Recoding
  • Critical Path Timing Delay
  • Back Annotation and Timing Closure
  • FIFOs