HOME       UP       PREV       NEXT (Protocol and Interface)  

Verilog RTL: Modules, Protocols and Interfaces

A hardware design consists of a number of modules interconnected by wires known as 'nets' (short for networks).

The interconnections between modules are typically structured as mating interfaces. An interface nominally consists of a number of terminals but these have no physical manifestation.

In a modern design flow, the protocol at an interface is ideally specified once in a master file that is imported for the synthesis of each module that sports it.

But a lot of low-level manual entry of RTL design is still (2017) used.

A clock domain is a set of modules and a clock generator. Within a synchronous clock domain all flip-flops have their clocks commoned.

30: (C) 2012-17, DJ Greaves, University of Cambridge, Computer Laboratory.   TAPE MISSING ICON