At the electrical/net level, a port consists of an interface and a protocol.
The interface is the set of pins or wires that connect the components.
The protocol defines the rules for changing the logic levels and the meaning of the associated data.
For example, an asynchronous interface might be defined in RTL as:
Transmit view of interface: Receive view of interface: // This is a four-phase asynchronous interface output [7:0] data; input [7:0] data; // where the idle state has strobe and ack output strobe; input strobe; // deasserted (low) and data is valid while input ack; output ack; // the strobe signal is asserted (high).
Ports commonly implement flow-control by handshaking. Data is only transferred when both the sender and receiver are happy to proceed.
A port generally has an idle state which it returns to between each transaction.
Sometimes the start of one transaction is immediately after the end of the previous, so the transition through the idle state is only nominal.
Sometimes the begining of one transaction is temporaly overlaid with the end of a previous, so the transition through idle state has no specific duration.
There are four basic clock strategies for an interface:
|Left Side||Right Side||Name|
|1. Clocked||Clocked||Synchronous (such as Xilinx LocalLink)|
|2. Clocked||Different clock||Clock Domain Crossing (see later)|
|3. Asynchronous||Clocked||Hybrid (swapped).|
|4. Asynchronous||Asynchronous||Asynchronous (such a four-phase parallel port)|
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