Everybody attending this course is expected to have previously studied RTL coding or at least taught themselves the basics before the course starts.
The Computer Laboratory has an online Verilog course you can follow: »Cambridge SystemVerilog Tutor
Please note that this now covers `System Verilog' whereas most of my examples are in plain old Verilog. There are a few, unimportant, syntax differences.
RTL is compiled to logic gate instances in a target library using a process called Logic Synthesis. RTL is also simulatable pre and post synthesis.
|3: (C) 2012-17, DJ Greaves, University of Cambridge, Computer Laboratory.|